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參數(shù)資料
| 型號： | AD5330BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 359K |
| 代理商： | AD5330BRU |
REV. 0
AD5330/AD5331/AD5340/AD5341
–17–
Bipolar Operation Using the AD5330/AD5331/AD5340/AD5341
The AD5330/AD5331/AD5340/AD5341 have been designed
for single supply operation, but bipolar operation is achievable
using the circuit shown in Figure 36. The circuit shown has been
configured to achieve an output voltage range of –5 V < V
O
<
+5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
V
O
= [(1 +
R
4/
R
3)
×
(
R
2/(
R
1 +
R
2)
×
(2
×
V
REF
×
D
/
2
N
)] –
R
4
×
V
REF
/
R
3
where:
D
is the decimal equivalent of the code loaded to the DAC,
N
is
DAC resolution and
V
REF
is the reference voltage input.
With:
V
REF
= 2.5 V
R1 = R3 = 10 k
R2 = R4 = 20 k
and V
DD
= 5 V.
V
OUT
= (10
×
D/2
N
) – 5
AD5330/AD5331/
AD5340/AD5341
GND
V
DD
= 5V
EXT
REF
V
OUT
AD780/REF192
WITH V
DD
= 5V
OR
AD589 WITH V
DD
= 2.5V
GND
V
IN
V
OUT
V
REF
V
DD
R3
10k
R1
10k
R2
20k
R4
20k
5V
+5V
–
5V
0.1 F
0.1 F
10 F
Figure 36. Bipolar Operation using the AD5330/AD5331/
AD5340/AD5341
Decoding Multiple AD5330/AD5331/AD5340/AD5341
The
CS
pin on these devices can be used in applications to decode
a number of DACs. In this application, all DACs in the system
receive the same data and
WR
pulses, but only the
CS
to one of
the DACs will be active at any one time, so data will only be
written to the DAC whose
CS
is low. If multiple AD5341s are
being used, a common HBEN line will also be required to
determine if the data is written to the high-byte or low-byte
register of the selected DAC.
The 74HC139 is used as a 2- to 4-line decoder to address any
of the DACs in the system. To prevent timing errors, the enable
input should be brought to its inactive state while the coded
address inputs are changing state. Figure 37 shows a diagram of a
typical setup for decoding multiple devices in a system. Once
data has been written sequentially to all DACs in a system, all the
DACs can be updated simultaneously using a common
LDAC
line. A common
CLR
line can also be used to reset all DAC
outputs to zero.
ENABLE
CODED
ADDRESS
1G
1A
1B
V
DD
V
CC
74HC139
DGND
1Y0
1Y1
1Y2
1Y3
HBEN
WR
LDAC
CLR
DATA
INPUTS
DATA
INPUTS
DATA
INPUTS
DATA
INPUTS
D
*AD5341 ONLY
HBEN*
WR
LDAC
CLR
CS
AD5330/AD5331/
AD5340/AD5341
HBEN*
WR
LDAC
CLR
CS
HBEN*
WR
LDAC
CLR
CS
HBEN*
WR
LDAC
CLR
CS
AD5330/AD5331/
AD5340/AD5341
AD5330/AD5331/
AD5340/AD5341
AD5330/AD5331/
AD5340/AD5341
Figure 37. Decoding Multiple DAC Devices
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|---|---|
| AD5331 | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
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| AD5335 | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
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