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參數(shù)資料
| 型號： | AD5326 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Rail-To-Rail,Voltage Output 12-Bit DACs(滿幅度電壓輸出雙12位D/A轉(zhuǎn)換器) |
| 中文描述： | 雙通道軌至軌電壓輸出12位DAC（滿幅度電壓輸出雙12位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 351K |
| 代理商： | AD5326 |
2
5
AD5306/16/26 Prelim Technical Information
Prelim B 9/98
on the state of the BUF bit in the input word to DAC D. It has an input range from 0V to V
DD
in
unbuffered mode and from 1V to V
DD
in buffered mode.
Active low control input which acts as a hardware Power-Down option. All DACs go into power-
down mode when this pin is tied low. The DAC outputs go into a high-impedance state or are tied
through a 100k
resistor to GND (depending on PD1 bit). The current consumption of the part
drops to 200nA @ 5V (50nA @ 3V).
Buffered analog output voltage from DAC D. The output amplifier has rail-to-rail operation.
Ground reference point for all circuitry on the part.
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input
shift register. It is a bi-directional open-drain data line which should be pulled to the supply with an
external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input
shift register. Clock rates of up to 400kbit/s can be accommodated in the I
2
C compatible interface.
Address Input. Sets the least significant bit of the 7-bit slave address.
Address Input. Sets the 2nd least significant bit of the 7-bit slave address.
PIN CONFIGURATIONS
1
3
14
2
TOP VIEW
(Not to Scale)
AD5306/16/26
15
16
4
13
5
12
6
7
8
11
10
9
LDAC
VDD
VREFA
VOUTA
VOUTB
VOUTC
VREFB
VREFC
VREFD
PD
VOUTD
GND
SDA
SCL
A0
A1
PIN FUNCTION DESCRIPTION
PIN NUMBERS
Pin
No. Mnemonic
Function
1
LDAC
Active low control input which transfers the contents of the input registers to their respective DAC
registers. Pulsing this pin low allows the simultaneous update of all DAC outputs
Power Supply Input. These parts can be operated from +2.5V to +5.5V and the supply should be
decoupled to GND.
Reference Input pin for DAC A. It may be configured as a buffered or an unbuffered input depending
on the state of the BUF bit in the input word to DAC A. It has an input range from 0V to V
DD
in
unbuffered mode and from 1V to V
DD
in buffered mode.
Buffered analog output voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered analog output voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered analog output voltage from DAC C. The output amplifier has rail-to-rail operation.
Reference Input pin for DAC B. It may be configured as a buffered or an unbuffered input depending
on the state of the BUF bit in the input word to DAC B. It has an input range from 0V to V
DD
in
unbuffered mode and from 1V to V
DD
in buffered mode.
Reference Input pin for DAC C. It may be configured as a buffered or an unbuffered input depending
on the state of the BUF bit in the input word to DAC C. It has an input range from 0V to V
DD
in
unbuffered mode and from 1V to V
DD
in buffered mode.
Reference Input pin for DAC D. It may be configured as a buffered or an unbuffered input depending
2
V
DD
3
V
REF
A
4
5
6
7
V
OUT
A
V
OUT
B
V
OUT
C
V
REF
B
8
V
REF
C
9
V
REF
D
10
PD
11
12
13
V
OUT
D
GND
SDA
14
SCL
15
16
A0
A1
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