- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375232 > AD526 (Analog Devices, Inc.) Software Programmable Gain Amplifier(軟件可編程增益放大器) PDF資料下載
參數(shù)資料
| 型號： | AD526 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Software Programmable Gain Amplifier(軟件可編程增益放大器) |
| 中文描述： | 軟件可編程增益放大器（軟件可編程增益放大器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 397K |
| 代理商： | AD526 |
AD526
REV. C
–7–
T HE ORY OF OPE RAT ION
T he AD526 is a complete software programmable gain amplifier
(SPGA) implemented monolithically with a drift-trimmed
BiFET amplifier, a laser wafer trimmed resistor network, JFET
analog switches and T T L compatible gain code latches.
A particular gain is selected by applying the appropriate gain
code (see T able I) to the control logic. T he control logic turns
on the JFET switch that connects the correct tap on the gain
network to the inverting input of the amplifier; all unselected
JFET gain switches are off (open). T he “on” resistance of the
gain switches causes negligible gain error since only the
amplifier’s input bias current, which is less than 150 pA, actu-
ally flows through these switches.
T he AD526 is capable of storing the gain code, (latched mode),
B, A0, A1, A2, under the direction of control inputs
CLK
and
CS
. Alternatively, the AD526 can respond directly to gain code
changes if the control inputs are tied low (transparent mode).
For gains of 8 and 16, a fraction of the frequency compensation
capacitance (C1 in Figure 32) is automatically switched out of
the circuit. T his increases the amplifier’s bandwidth and im-
proves its signal settling time and slew rate.
Figure 32. Simplified Schematic of the AD526
T RANSPARE NT MODE OF OPE RAT ION
In the transparent mode of operation, the AD526 will respond
directly to level changes at the gain code inputs (A0, A1, A2) if
B is tied high and both
CS
and
CLK
are allowed to float low.
After the gain codes are changed, the AD526’s output voltage
typically requires 5.5
μ
s to settle to within 0.01% of the final
value. Figures 26 to 29 show the performance of the AD526 for
positive gain code changes.
Figure 33. Transparent Mode
LAT CHE D MODE OF OPE RAT ION
T he latched mode of operation is shown in Figure 34. When
either
CS
or
CLK
go to a logic “1,” the gain code (A0, A1, A2,
B) signals are latched into the registers and held until both
CS
and
CLK
return to “0.”
Unused
CS
or
CLK
inputs should be tied
to ground .
T he
CS
and
CLK
inputs are functionally and electri-
cally equivalent.
Figure 34. Latched Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5290 | Compact +30V/【15V 256-Position Digital Potentiometer |
| AD5290EVAL | Compact +30V/【15V 256-Position Digital Potentiometer |
| AD5290YRMZ10 | Compact +30V/【15V 256-Position Digital Potentiometer |
| AD5290YRMZ100 | Compact +30V/【15V 256-Position Digital Potentiometer |
| AD5290YRMZ100-RL7 | Compact +30V/【15V 256-Position Digital Potentiometer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5260 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit Dual Nonvolatile Memory Digital Potentiometer |
| AD5260_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1-/2-Channel 15 V Digital Potentiometer |
| AD5260BRU20 | 制造商:Analog Devices 功能描述:Digital Potentiometer 256POS 20KOhm Single 14-Pin TSSOP 制造商:Analog Devices 功能描述:IC DIGITAL POTENTIOMETER 8-BIT |
| AD5260BRU200 | 制造商:Analog Devices 功能描述:Digital Potentiometer 256POS 200KOhm Single 14-Pin TSSOP 制造商:Analog Devices 功能描述:IC DIGITAL POTENTIOMETER 8-BIT |
| AD5260BRU200-REEL7 | 制造商:Analog Devices 功能描述:Digital Potentiometer 256POS 200KOhm Single 14-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:8-BIT SPI DIG POT - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。