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參數(shù)資料
| 型號： | AD526 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Software Programmable Gain Amplifier(軟件可編程增益放大器) |
| 中文描述： | 軟件可編程增益放大器（軟件可編程增益放大器） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 397K |
| 代理商： | AD526 |
AD526
REV. C
–10–
OFFSE T NULLING WIT H A D/A CONVE RT E R
Figure 41 shows the AD526 with offset nulling accomplished
with an 8-bit D/A converter (AD7524) circuit instead of the po-
tentiometer shown in Figure 39. T he calibration procedure is
the same as before except that instead of adjusting the potenti-
ometer, the D/A converter corrects for the offset error. T his
calibration circuit has a number of benefits in addition to elimi-
nating the trimpot. T he most significant benefit is that calibra-
tion can be under the control of a microprocessor and therefore
can be implemented as part of an autocalibration scheme. Sec-
ondly, dip switches or RAM can be used to hold the 8-bit word
after its value has been determined. In Figure 42 the offset null
sensitivity, at a gain of 16, is 80
μ
V per LSB of adjustment,
which guarantees dc accuracy to the 16-bit performance level.
Figure 41. Offset Nulling Using a DAC
FLOAT ING-POINT CONVE RSION
High resolution converters are used in systems to obtain high
accuracy, improve system resolution or increase dynamic range.
T here are a number of high resolution converters available with
throughput rates of 66.6 kHz that can be purchased as a single
component solution; however in order to achieve higher through-
put rates, alternative conversion techniques must be employed.
A floating point A/D converter can improve both throughput
rate and dynamic range of a system.
In a floating point A/D converter (Figure 42), the output data is
presented as a 16-bit word, the lower 12 bits from the A/D con-
verter form the mantissa and the upper 4 bits from the digital
signal used to set the gain form the exponent. T he AD526 pro-
grammable gain amplifier in conjunction with the comparator
circuit scales the input signal to a range between half scale and
full scale for the maximum usable resolution.
T he A/D converter diagrammed in Figure 42 consists of a pair
of AD585 sample/hold amplifiers, a flash converter, a five-range
programmable gain amplifier (the AD526) and a fast 12-bit A/D
converter (the AD7572). T he floating-point A/D converter
achieves its high throughput rate of 125 kHz by overlapping the
acquisition time of the first sample/hold amplifier and the set-
tling time of the AD526 with the conversion time of the A/D
converter. T he first sample/hold amplifier holds the signal for
the flash autoranger, which determines which binary quantum
the input falls within, relative to full scale. Once the AD526 has
settled to the appropriate level, then the second sample/hold
amplifier can be put into hold which holds the amplified signal
while the AD7572 perform its conversion routine. T he acquisi-
tion time for the AD585 is 3
μ
s, and the conversion time for the
AD7572 is 5
μ
s for a total of 8
μ
s, or 125 kHz. T his performance
relies on the fast settling characteristics of the AD526 after the
flash autoranging (comparator) circuit quantizes the input sig-
nal. A 16-bit register holds the 3-bit output from the flash
autoranger and the 12-bit output of the AD7572.
T he A/D converter in Figure 42 has a dynamic range of 96 dB.
T he dynamic range of a converter is the ratio of the full-scale
input range to the LSB value. With a floating-point A/D con-
verter the smallest value LSB corresponds to the LSB of the
monolithic converter divided by the maximum gain of the PGA.
T he floating point A/D converter has a full-scale range of 5 V, a
maximum gain of 16 V/V from the AD526 and a 12-bit A/D
converter; this produces:
LSB = ([FSR/2
N
]/Gain) = ([5 V/4096]/16) = 76
μ
V. T he
dynamic range in dBs is based on the log of the ratio of the
full-scale input range to the LSB; dynamic range = 20 log
(5 V/76
μ
V) = 96 dB.
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