參數(shù)資料
型號(hào)： AD524BDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 0K
描述： IC AMP INST 1MHZ PREC LN 16CDIP
標(biāo)準(zhǔn)包裝： 23
放大器類(lèi)型： 儀表
電路數(shù)： 1
轉(zhuǎn)換速率： 5 V/µs
增益帶寬積： 1MHz
-3db帶寬： 1MHz
電流 - 輸入偏壓： 25nA
電壓 - 輸入偏移： 100µV
電流 - 電源： 3.5mA
電壓 - 電源，單路/雙路(±)： ±6 V ~ 18 V
工作溫度： -25°C ~ 85°C
安裝類(lèi)型： 通孔
封裝/外殼： 16-CDIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 16-CDIP 側(cè)面銅焊
包裝： 管件
產(chǎn)品目錄頁(yè)面： 770 (CN2011-ZH PDF)
AD524
Rev. F | Page 17 of 28
The AD524 can also be configured to provide gain in the output
stage. Figure 37 shows an H pad attenuator connected
to the reference and sense lines of the AD524. R1, R2, and R3
should be made as low as possible to minimize the gain variation
and reduction of CMRR. Varying R2 precisely sets the gain
without affecting CMRR. CMRR is determined by the match
of R1 and R3.
G = 100
G = 1000
G =
G = 10
AD524
+INPUT
–INPUT
+VS
–VS
(R1 + R2 + R3)||RL ≥ 2k
VOUT
RL
R1
2.26k
R2
5k
R3
2.26k
(R2||40k) + R1 + R3
(R2||40k)
RG1
RG2
1
16
13
12
11
3
2
8
7
10
6
9
0
0500
-037
Figure 37. Gain of 2000
Table 4. Output Gain Resistor Values
Output Gain
R2
R1, R3
Nominal Gain
2
5 kΩ
2.26 kΩ
2.02
5
1.05 kΩ
2.05 kΩ
5.01
10
1 kΩ
4.42 kΩ
10.1
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the
input transistors of a dc amplifier. Bias currents are an
additional source of input error and must be considered in
a total error budget. The bias currents, when multiplied by
the source resistance, appear as an offset voltage. What is of
concern in calculating bias current errors is the change in bias
current with respect to signal voltage and temperature. Input
offset current is the difference between the two input bias
currents. The effect of offset current is an input offset voltage
whose magnitude is the offset current times the source
impedance imbalance.
AD524
LOAD
+
–
TO POWER
SUPPLY
GROUND
+VS
–VS
2
3
11
12
13
16
1
8
7
10
6
9
00500
-038
Figure 38. Indirect Ground Returns for Bias Currents—Transformer Coupled
AD524
LOAD
+
–
+VS
–VS
TO POWER
SUPPLY
GROUND
2
8
7
10
6
9
3
11
12
13
16
1
005
00-
039
Figure 39. Indirect Ground Returns for Bias Currents—Thermocouple
AD524
LOAD
+VS
–VS
TO POWER
SUPPLY
GROUND
2
8
7
10
6
9
3
11
12
13
16
1
+
–
0
050
0-
04
0
Figure 40. Indirect Ground Returns for Bias Currents–AC-Coupled
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents charge stray capacitances, causing the
output to drift uncontrollably or to saturate. Therefore, when
amplifying floating input sources such as transformers and
thermocouples, as well as ac-coupled sources, there must still
be a dc path from each input to ground.
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. Common-mode
rejection ratio (CMRR) is a ratio expression whereas common-
mode rejection (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due
to varied stray capacitances or cable capacitances. In many
applications, shielded cables are used to minimize noise. This
technique can create common-mode rejection errors unless the
shield is properly driven. Figure 41 and Figure 42 show active
data guards that are configured to improve ac common-mode
rejection by bootstrapping the capacitances of the input cabling,
thus minimizing differential phase shift.
REFERENCE
AD524
100
AD711
G = 100
+INPUT
–INPUT
VOUT
+VS
–VS
+
–
RG2
1
12
3
2
8
10
9
6
7
0
0500-
041
Figure 41. Shield Driver, G ≥ 100
REFERENCE
AD524
100
AD712
+INPUT
–INPUT
100
VOUT
+VS
–VS
RG1
RG2
–VS
–
+
1
16
12
3
2
7
6
9
10
8
005
00-
042
Figure 42. Differential Shield Driver
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