參數(shù)資料
型號： AD524BDZ
廠商： Analog Devices Inc
文件頁數(shù)： 8/28頁
文件大?。?/td> 0K
描述： IC AMP INST 1MHZ PREC LN 16CDIP
標(biāo)準(zhǔn)包裝： 23
放大器類型： 儀表
電路數(shù)： 1
轉(zhuǎn)換速率： 5 V/µs
增益帶寬積： 1MHz
-3db帶寬： 1MHz
電流 - 輸入偏壓： 25nA
電壓 - 輸入偏移： 100µV
電流 - 電源： 3.5mA
電壓 - 電源，單路/雙路(±)： ±6 V ~ 18 V
工作溫度： -25°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 16-CDIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 16-CDIP 側(cè)面銅焊
包裝： 管件
產(chǎn)品目錄頁面： 770 (CN2011-ZH PDF)
AD524
Rev. F | Page 16 of 28
Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is the component
of offset that is directly proportional to gain, that is, input offset
as measured at the output at G = 100 is 100 times greater than at
G = 1. Output offset is independent of gain. At low gains, output
offset drift is dominant, at high gains, input offset drift dominates.
Therefore, the output offset voltage drift is normally specified as
drift at G = 1 (where input effects are insignificant), whereas
input offset voltage drift is given by drift specification at a high
gain (where output offset effects are negligible). All input
related numbers are referred to the input (RTI) that is the effect
on the output is G times larger. Voltage offset vs. power supply
is also specified at one or more gain settings and is also RTI.
By separating these errors, one can evaluate the total error
independent of the gain setting used. In a given gain configura-
tion, both errors can be combined to give a total error referred
to the input (RTI) or output (RTO) by the following formulas:
Total error RTI = input error + (output error/gain)
Total error RTO = (gain × input error) + output error
As an illustration, a typical AD524 might have a +250 μV
output offset and a 50 μV input offset. In a unity gain
configuration, the total output offset would be 200 μV or
the sum of the two. At a gain of 100, the output offset would
be 4.75 mV or: +250 μV + 100(50 μV) = 4.75 mV.
The AD524 provides for both input and output offset adjustment.
This simplifies very high precision applications and minimizes
offset voltage changes in switched gain applications. In such
applications, the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.
GAIN
The AD524 has internal high accuracy pretrimmed resistors
for pin programmable gains of 1, 10, 100, and 1000. One of the
preset gains can be selected by pin strapping the appropriate
gain terminal and RG2 together (for G = 1, RG2 is not connected).
AD524
G = 10
G = 100
G = 1000
+INPUT
–INPUT
VOUT
OUTPUT
SIGNAL
COMMON
–VS
INPUT
OFFSET
NULL
+VS
10k
RG1
RG2
1
16
13
12
11
3
2
8
4
5
10
9
6
7
005
00-
034
Figure 34. Operating Connections for G = 100
The AD524 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between
Pin 3 and Pin 16 (see Figure 35), which programs the gain
according to the following formula:
1
k
40
=
Ω
=
G
R
G
For best results, RG should be a precision resistor with a low
temperature coefficient. An external RG affects both gain
accuracy and gain drift due to the mismatch between it and
the internal thin-film resistors. Gain accuracy is determined
by the tolerance of the external RG and the absolute accuracy
of the internal resistors (±20%). Gain drift is determined by the
mismatch of the temperature coefficient of RG and the tempera-
ture coefficient of the internal resistors (50 ppm/°C typical).
40,000
2.105
G =
+ 1 = 20 ±20%
AD524
REFERENCE
1k
+INPUT
–INPUT
2.105k
1.5k
VOUT
+VS
–VS
RG1
RG2
1
16
8
7
6
9
10
13
12
11
3
2
00500
-03
5
Figure 35. Operating Connections for G = 20
The second method uses the internal resistors in parallel with
an external resistor (see Figure 36). This technique minimizes
the gain adjustment range and reduces the effects of tempera-
ture coefficient sensitivity.
G =
G = 10
AD524
REFERENCE
+INPUT
–INPUT
4k
*R|G = 10 = 4444.44
*R|G = 100 = 404.04
*R|G = 1000 = 40.04
*NOMINAL (±20%)
VOUT
40,000
4000||4444.44
+ 1 = 20 ±17%
+VS
–VS
RG1
RG2
1
16
13
12
11
3
2
8
7
10
6
9
00500
-03
6
Figure 36. Operating Connections for G = 20, Low Gain
Temperature Coefficient Technique
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