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參數(shù)資料
| 型號(hào)： | AD5232BRUZ50-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL DUAL 256POS 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 600 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-AD5232-10EBZ-ND - BOARD EVALUATION FOR AD5232-10 |
AD5232
Data Sheet
Rev. C | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
SDI
SDO
GND
W1
A1
VSS
CLK
B1
16
15
14
13
12
11
10
9
CS
PR
WP
W2
B2
A2
VDD
RDY
AD5232
TOP VIEW
(Not to Scale)
02618-
004
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No.
Mnemonic
Description
1
CLK
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
2
SDI
Serial Data Input. The MSB is loaded first.
3
SDO
Serial Data Output. This open-drain output requires an external pull-up resistor. Command Instruction 9 and Command
Instruction 10 activate the SDO output (see Table 8). Other commands shift out the previously loaded SDI bit pattern
delayed by 16 clock pulses, allowing daisy-chain operation of multiple packages.
4
GND
Ground, Logic Ground Reference.
5
VSS
Negative Power Supply. Connect to 0 V for single-supply applications.
6
A1
Terminal A of RDAC1.
7
W1
Wiper Terminal W of RDAC1, ADDR (RDAC1) = 0x0.
8
B1
Terminal B of RDAC1.
9
B2
Terminal B of RDAC2.
10
W2
Wiper Terminal W of RDAC2, ADDR (RDAC2) = 0x1.
11
A2
Terminal A of RDAC2.
12
VDD
Positive Power Supply.
13
WP
Write Protect. When active low, WP prevents any changes to the present register contents, except PR, Command
Instruction 1, and Command Instruction 8, which refresh the RDACx register from EEMEM. Execute an NOP instruction
(Command Instruction 0) before returning WP to logic high.
14
PR
Hardware Override Preset. Refreshes the scratch pad register with current contents of the EEMEMx register. Factory
default loads Midscale 0x80 until EEMEMx is loaded with a new value by the user (PR is activated at the logic high
transition).
15
CS
Serial Register Chip Select, Active Low. Serial register operation takes place when CS returns to logic high.
16
RDY
Ready. This active-high, open-drain output requires a pull-up resistor. Identifies completion of Command Instruction 2,
Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and PR.
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