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參數(shù)資料
| 型號： | AD5232BRUZ50-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL DUAL 256POS 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 600 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-AD5232-10EBZ-ND - BOARD EVALUATION FOR AD5232-10 |
AD5232
Data Sheet
Rev. C | Page 20 of 24
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage pro-
portional to the input voltage applied to a given terminal. For
example, connecting Terminal A to 5 V and Terminal B to GND
produces an output voltage at the wiper that can be any value
from 0 V to 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A to Terminal B, divided by the 2N
position resolution of the potentiometer divider. The general
equation defining the output voltage with respect to ground for
any given input voltage applied to Terminal A to Terminal B is
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
×
+
×
=
)
(
)
(
)
(
(3)
where RWB(D) can be obtained from Equation 1 and RWA(D)
can be obtained from Equation 2.
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors,
not the absolute value; therefore, the drift improves to 15 ppm/°C.
There is no voltage polarity restriction between Terminal A,
Terminal B, and Wiper Terminal W as long as the terminal voltage
(VTERM) stays within VSS < VTERM < VDD.
OPERATION FROM DUAL SUPPLIES
The AD5232 can be operated from dual supplies, enabling
control of ground-referenced ac signals (see Figure 42 for
a typical circuit connection).
AD5232
VSS
GND
SDI
CLK
SS
SCLK
MOSI
GND
VDD
±2V p-p
±1V p-p
VDD
+2.5V
–2.5V
CS
02618-
042
MicroConverter
Figure 42. Operation from Dual Supplies
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. When
configured as a potentiometer divider, the 3 dB bandwidth of
the AD5232BRU10 (10 k resistor) measures 500 kHz at half
scale. Figure 14 provides the large signal BODE plot character-
istics of the three resistor versions: 10 k, 50 k, and 100 k (see
Figure 43 for a parasitic simulation model of the RDAC circuit).
A
W
02618-
043
B
RDAC
10k
CA
45pF
CB
45pF
CW
60pF
Figure 43. RDAC Circuit Simulation Model for RDACx = 10 k
The following code provides a macro model net list for the
10 k RDAC:
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,B)
*
CA A 0 {45E-12}
RAW A W {(1-DW/256)*RDAC+50}
CW W 0 60E-12
RBW W B {DW/256*RDAC+50}
CB B 0 {45E-12}
*
.ENDS DPOT
APPLICATION PROGRAMMING EXAMPLES
The command sequence examples shown in Table 14 to Table 18
have been developed to illustrate a typical sequence of events
for the various features of the AD5232 nonvolatile digital poten-
tiometer. Table 14 illustrates setting two digital potentiometers
to independent data values.
Table 14.
SDI
SDO
Action
0xB140
0xXXXX
Loads 0x40 data into the RDAC2 register;
Wiper W2 moves to 1/4 full-scale position.
0xB080
0xB140
Loads 0x80 data into the RDAC1 register;
Wiper W1 moves to 1/2 full-scale position.
Table 15 illustrates the active trimming of one potentiometer,
followed by a save to nonvolatile memory (PCB calibrate).
Table 15.
SDI
SDO
Action
0xB040
0xXXXX
Loads 0x40 data into the RDAC1 register;
Wiper W1 moves to 1/4 full-scale position.
0xE0XX
0xB040
Increments the RDAC1 register by 1, to 0x41;
Wiper W1 moves one resistor segment
away from Terminal B.
0xE0XX
Increments the RDAC1 register by 1, to 0x42;
Wiper W1 moves one more resistor segment
away from Terminal B. Continue until
desired the wiper position is reached.
0x20XX
0xE0XX
Saves the RDAC1 register data into the
corresponding nonvolatile EEMEM1
memory: ADDR = 0x0.
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