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參數(shù)資料
| 型號： | AD5170EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | 256-Position Two-Time Programmable I2C Digital Potentiometer |
| 中文描述： | 256位二時間的I2C可編程數(shù)字電位器 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 900K |
| 代理商： | AD5170EVAL |
AD5170
TIMING CHARACTERISTICS — 2.5 k
, 10 k
, 50 k
, 100 k
VERSIONS
V
DD
= 5 V ± 10% or 3 V ± 10%, V
A
= V
DD
; V
B
= 0 V, –40°C < T
A
< +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
I
2
C INTERFACE TIMING CHARACTERISTICS
1
(Specifications apply to all parts)
SCL Clock Frequency
f
SCL
t
BUF
Bus Free Time between STOP and START
t
1
t
HD;STA
Hold Time (Repeated START)
t
2
Rev. A | Page 5 of 24
Conditions
Min
1.3
0.6
Typ
Max
400
Unit
kHz
μs
μs
After this period, the first clock
pulse is generated.
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated START Condition
t
HD;DAT
Data Hold Time
2
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL Signals
t
SU;STO
Setup Time for STOP Condition
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1.3
0.6
0.6
100
0.6
0.9
300
300
μs
μs
μs
μs
ns
ns
ns
μs
1
See timing diagrams for locations of measured values.
2
The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
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