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參數(shù)資料
| 型號： | AD5165 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
| 中文描述： | 256位置，超低功耗1.8 V邏輯級數(shù)字電位器 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 569K |
| 代理商： | AD5165 |
AD5165
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
Rev. 0 | Page 14 of 16
A
V
I
W
B
V
O
0
Figure 38. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V
up to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminals A and B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at V
W
with respect to ground for any
valid input voltage applied to terminals A and B is
B
A
W
V
D
V
D
D
V
256
256
256
)
(
+
=
(3)
A more accurate calculation, which includes the effect of wiper
resistance,
V
W
,
is
B
AB
WA
R
A
AB
WB
R
W
V
D
R
V
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
WA
and R
WB
and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
3-WIRE SERIAL BUS DIGITAL INTERFACE
The AD5165 contains a 3-wire digital interface (SDI, CS, and
CLK). The 8-bit serial word must be loaded MSB first. The
format of the word is shown in Table 5.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is high, the clock
loads data into the serial register on each positive clock edge,
as shown in Figure 34.
The data setup and data hold times in the specifications table
determine the valid timing requirements. The AD5165 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic low.
Extra MSB bits are ignored.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, shown in Figure 39 and
Figure 40. This applies to the digital input pins SDI, CLK,
and CS.
LOGIC
340
GND
0
Figure 39. ESD Protection of Digital Pins
A, B, W
GND
0
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5165 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer oper-
ation. Supply signals present on terminals A, B, and W that
exceed V
DD
or GND are clamped by the internal forward-biased
diodes, as shown in Figure 41.
GND
A
W
B
V
DD
0
Figure 41. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 41), it is important to
power V
DD
/GND before applying any voltage to terminals A, B,
and W; otherwise, the diode is forward biased such that V
DD
is
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
DD
, digital inputs, and then V
A
, V
B
, and V
W
. The relative
order of powering V
A
, V
B
, V
W
, and the digital inputs is not
important as long as they are powered after V
DD
/GND.
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| AD5165BUJZ100-R2 | 功能描述:IC DGTL POT 100K LP TSOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT |
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