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參數(shù)資料
| 型號(hào)： | AD5060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Full Accurate 14/16 Bit Vout nanoDac Buffered, 3V/5V, Sot 23 |
| 中文描述： | 全面準(zhǔn)確14/16輸出電壓nanoDAC系列緩沖，3V/5V，索23位 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 829K |
| 代理商： | AD5060 |
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Preliminary Technical Data
AD5040/AD5060
Rev. PrC | Page 13 of 17
Figure 22. AD5060 Input Register Contents
Figure 22. AD5040 Input Register Contents
SYNC Interrupt
For the AD5060, in normal write sequence, the SYNC line is
kept low for at least 24 falling edges of SCLK and the DAC is
updated on the 24th falling edge. However, if SYNC is brought
high before the 24th falling edge this acts as an interrupt to the
write sequence. The shift register is reset and the write
sequence is seen as invalid. Neither an update of the DAC
register contents or a change in the operating mode occurs—
see Figure 23. For the AD5040, the same applies to the 16
th
clock edge.
Power-On-Reset
The AD5040/AD5060 contains a power-on-reset circuit that
controls the output voltage during power-up. The DAC register
is filled with zeros and the output voltage is zero volts/mid-
scale. It remains there until a valid write sequence is made to
the DAC. This is useful in applications where it is important to
know the state of the output of the DAC while it is in the
process of powering up.
Software Reset.
The AD5040/AD5060 can be put into software reset by setting
all in the Dac register to one. For the AD5060 this includes
writing ones to bits D23-D16, which in not the normal mode of
operation.
Note: The
SYNC Interrupt command cannot be
performed if a software reset command is started.
Power-Down Modes
The AD5040/AD5060 contains four separate modes of
operation. These modes are software-programmable by setting
two bits (PD1 and PD0) in the control register. Table I shows
how the state of the bits corresponds to the mode of operation
of the device.
Table I. Modes of Operation for the
AD5040/AD5060
PD1
0
0
1
1
PD0
0
1
0
1
Operating Mode
Normal Operation
Power-Down Mode
TRI-STATE
100 k
to GND
1 k
to GND *
*Not available for the AD5040; Reserved mode.
When both bits are set to 0, the part works normally with its
normal power consumption. However, for the three power-
down modes, the supply current falls to 200 nA at 5 V (50 nA at
3 V). Not only does the supply current fall but the
output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This
has the advantage that the output impedance of the part
is known while the part is in power-down mode.
There are three different options. The output is
connected internally to GND through a
1k
resistor, a
100 k
resistor
or it is left open-circuited (Three-State). The output stage is illustrated in
Figure 24.
Figure 24. Output Stage During Power-Down
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