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參數(shù)資料
| 型號(hào)： | AD5060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Full Accurate 14/16 Bit Vout nanoDac Buffered, 3V/5V, Sot 23 |
| 中文描述： | 全面準(zhǔn)確14/16輸出電壓nanoDAC系列緩沖，3V/5V，索23位 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 829K |
| 代理商： | AD5060 |
AD5040/5060
Preliminary Technical Data
GENERAL DESCRIPTION
The AD5040/AD5060 are single 14/16-bit, serial input, voltage
output DACs. The AD5040 operates from a supply voltage of
2.7-5.5 V. The AD5060 operates from either a 3V or 5V supply.
Data is written to the AD5040 in a 14-bit word format and to
the AD5060 with a 16-bit word via a 3-wire serial interface
Rev. PrC | Page 12 of 17
The AD5040/AD5060 incorporates a power-on reset circuit,
which ensures that the DAC output powers up to 0 V or mid-
scale. The device also has a software power-down mode pin,
which reduces the typical current consumption to 50nA at 3V.
DAC Architecture
The DAC architecture of the AD5040/AD5060 consists of two
matched DAC sections. A simplifed circuit diagram is shown in
Figure X The four MSBs of the 16-bit data word are decoded to
drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either AGND or VREF. The
remaining 12 bits of thedata word drive switches S0 to S11 of a
12-bit voltage modeR-2R ladder network.
Figure X. DAC Ladder Structure
Reference Buffer
The AD5060 operates with an external reference. The
reference input (REFIN) has an input range of up to Vdd.
This input voltage is then used to provide a buffered
reference for the DAC core
SERIAL INTERFACE
The AD5040/AD5060 (16/24 bit word write) have a
three-wire serial interface (SYNC, SCLK and DIN),
which is compatible with SPI, QSPI and
MICROWIRE interface standards as well as most DSPs. See
Figure 1 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 16/24-bit shift
register on the falling edge of SCLK. The serial clock frequency
can be as high as 30 MHz, making the
se parts
compatible with
high speed DSPs. On the 16
th
/24
th
falling clock edge, the last
data bit is clocked in and the programmed function is executed
(i.e., a change in DAC register contents and/or a change in the
mode of operation). At this stage, the SYNC line may be kept
low or be brought high. In either case, it must be brought high
for a minimum of 33 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when VIN = 1.8 V than it
does when VIN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation of the part. As
is mentioned above, however, it must be brought high again
just before the next write sequence.
Input Shift Register
The input shift register is 16/24 bits wide (see Figure 22/23).
D23-D16 are set to zero for normal operation in the AD5060.
For the AD5060 D17, D16 are control bits that control which
mode of operation the part is in (normal mode or any one of
three power-down modes). There is a more complete
description of the various modes in the Power-Down
Modes section. The next sixteen bits are the data bits. These
are transferred to the DAC register on the 24th falling edge of SCLK.
For the AD5040 D15, D14 are control bits that control which
mode of operation the part is in (normal mode or any one of
three power-down modes). The next fourteen bits are the data
bits. These are transferred to the DAC register on the 16th falling edge of
SCLK.
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