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參數(shù)資料
| 型號： | AD420 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Serial Input 16-Bit 4 mA-20 mA, 0 mA-20 mA DAC |
| 中文描述： | 串行輸入16位四毫安- 20毫安，○毫安- 20毫安援 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 144K |
| 代理商： | AD420 |
REV. F
–6–
AD420
THEORY OF OPERATION
The AD420 uses a sigma-delta (
Σ
) architecture to carry out
the digital-to-analog conversion. This architecture is particularly
well suited for the relatively low bandwidth requirements of the
industrial control environment because of its inherent monoto-
nicity at high resolution.
In the AD420 a second order modulator is used to keep com-
plexity and die size to a minimum. The single bit stream from
the modulator controls a switched current source that is then
filtered by two, continuous time resistor-capacitor sections. The
capacitors are the only external components that have to be
added for standard current-out operation. The filtered current is
amplified and mirrored to the supply rail so that the application
simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA
current source output with respect to ground. The AD420 is
manufactured on a BiCMOS process that is well suited to imple-
menting low voltage digital logic with high performance and
high voltage analog circuitry.
The AD420 can also provide a voltage output instead of a cur-
rent loop output if desired. The addition of a single external
amplifier allows the user to obtain 0 V–5 V, 0 V–10 V,
±
5 V, or
±
10 V.
The AD420 has a loop fault detection circuit that warns if the
voltage at I
OUT
attempts to rise above the compliance range, due
to an open-loop circuit or insufficient power supply voltage. The
FAULT DETECT is an active low open drain signal so that one
can connect several AD420s together to one pull-up resistor for
global error detection. The pull-up resistor can be tied to the
V
LL
pin, or an external +5 V logic supply.
The I
OUT
current is controlled by a PMOS transistor and
internal amplifier as shown in the functional block diagram. The
internal circuitry that develops the fault output avoids using a
comparator with “window limits” since this would require an
actual output error before the FAULT DETECT output becomes
active. Instead, the signal is generated when the internal ampli-
fier in the output stage of the AD420 has less than approximately
one volt remaining of drive capability (when the gate of the
output PMOS transistor nearly reaches ground). Thus the
FAULT DETECT output activates slightly before the compli-
ance limit is reached. Since the comparison is made within the
feedback loop of the output amplifier, the output accuracy is
maintained by its open-loop gain, and no output error occurs
before the fault detect output becomes active.
The three-wire digital interface, comprising DATA IN, CLOCK,
and LATCH, interfaces to all commonly used serial micropro-
cessors without the addition of any external glue logic. Data is
loaded into an input register under control of CLOCK and is
loaded to the DAC when LATCH is strobed. If a user wants to
minimize the number of galvanic isolators in an intrinsically safe
application, the AD420 can be configured to run in “asynchro-
nous” mode. This mode is selected by connecting the LATCH
pin to V
CC
through a current limiting resistor. The data must
then be combined with a start and stop bit to “frame” the infor-
mation and trigger the internal LATCH signal.
AD420
V
CC
23
4k
V
40
V
BOOST
I
OUT
V
OUT
FAULT
DETECT
GND
CAP 1
OFFSET
TRIM
V
LL
REF OUT
REF IN
DATA OUT
CLEAR
LATCH
CLOCK
DATA IN
RANGE
SELECT 1
RANGE
SELECT 2
1.25k
V
REFERENCE
CLOCK
16-BIT
DAC
DATA I/P
REGISTER
19
20
21
14
15
16
17
18
6
7
8
9
10
11
2
3
4
5
SWITCHED
CURRENT
SOURCES
AND
FILTERING
CAP 2
Figure 4. Functional Block Diagram
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