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參數(shù)資料
| 型號(hào)： | AD420 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Serial Input 16-Bit 4 mA-20 mA, 0 mA-20 mA DAC |
| 中文描述： | 串行輸入16位四毫安- 20毫安，○毫安- 20毫安援 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 144K |
| 代理商： | AD420 |
REV. F
–4–
AD420
Timing Requirements
(T
A
= –40
8
C to +85
8
C, V
CC
= +12 V to +32 V)
THREE-WIRE INTERFACE
CLOCK
DATA IN
LATCH
DATA OUT
CLOCK
DATA IN
LATCH
DATA OUT
WORD "N"
WORD "N + 1"
WORD "N – 1"
WORD "N"
1
0
1 1
0 0
1
0 0
1 1 1
0 0
1 1
1
0 0
1
(
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
(
1 0
1 1
B
B
B
B
t
CK
t
CL
t
CH
t
DS
t
DH
t
DW
t
LD
t
LL
t
LH
t
SD
Figure 2. Timing Diagram for Three-Wire Interface
Table II. Timing Specification for Three-Wire Interface
Parameter
Label
Limit
Units
Data Clock Period
Data Clock Low Time
Data Clock High Time
Data Stable Width
Data Setup Time
Data Hold Time
Latch Delay Time
Latch Low Time
Latch High Time
Serial Output Delay Time
Clear Pulsewidth
t
CK
t
CL
t
CH
t
DW
t
DS
t
DH
t
LD
t
LL
t
LH
t
SD
t
CLR
300
80
80
125
40
5
80
80
80
225
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
Three-Wire Interface Fast Edges on Digital Input
With a fast rising edge (<10 ns) on one of the serial inputs
(CLOCK, DATA IN, LATCH) while another input is logic
high, the part may be triggered into a test mode and the con-
tents of the data register may become corrupted, which may
result in the output being loaded with an incorrect value. If fast
edges are expected on the digital input lines, it is recommended
that the latch line remain at Logic 0 during serial loading of the
DAC. Similarly, the clock line should remain low during updates
of the DAC via the latch pin. Alternatively, the addition of
small value capacitors on the digital lines will slow down the
edge.
CLOCK
DATA IN
CLOCK
DATA IN
t
ADH
t
ACK
t
ADW
t
ACL
t
ADS
S
B
0
1
1
0
0
B
B
B
1
B
S
B
N
S
B
(INTERNALLY GENERATED LATCH)
EXPANDED TIME VIEW BELOW
CLOCK COUNTER STARTS HERE
CONFIRM START BIT
SAMPLE BIT 15
0
1
2
8
16
24
START BIT
DATA BIT 15
BIT 14
EXPANDED TIME VIEW BELOW
t
ACH
CLOCK
DATA IN
Figure 3. Timing Diagram for Asynchronous Interface
Table III. Timing Specifications for Asynchronous Interface
Parameter
Label
Limit Units
Asynchronous Clock Period
Asynchronous Clock Low Time
Asynchronous Clock High Time
Data Stable Width (Critical Clock Edge) t
ADW
Data Setup Time (Critical Clock Edge)
Data Hold Time (Critical Clock Edge)
Clear Pulsewidth
t
ACK
t
ACL
t
ACH
400
50
150
300
50
20
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
ADS
t
ADH
t
CLR
ASYNCHRONOUS INTERFACE
Note in the timing diagram for asynchronous mode operation
each data word is “framed” by a START (0) bit and a STOP
(1) bit. The data timing is with respect to the rising edge of the
CLOCK at the center of each bit cell. Bit cells are 16 clocks
long, and the first cell (the START bit) begins at the first clock
following the leading (falling) edge of the START bit. Thus the
MSB (D15) is sampled 24 clock cycles after the beginning of
the START bit, D14 is sampled at clock number 40, and so on.
During any “dead time” before writing the next word the
DATA IN pin must remain at Logic 1.
The DAC output updates when the STOP bit is received. In
the case of a “framing error” (the STOP bit sampled as a 0) the
AD420 will output a pulse at the DATA OUT pin one clock
period wide during the clock period subsequent to sampling the
STOP bit. The DAC output will not update if a “framing error”
is detected.
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