參數(shù)資料
型號: AD2S93AP
廠商: ANALOG DEVICES INC
元件分類: 位置變換器
英文描述: Aluminum Electrolytic Capacitor; Capacitor Type:Industrial Grade; Voltage Rating:350VDC; Capacitor Dielectric Material:Aluminum Electrolytic; Operating Temperature Range:-40 C to +85 C; Capacitance:160uF RoHS Compliant: Yes
中文描述: LVDT OR RVDT TO DIGITAL CONVERTER, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 5/12頁
文件大小: 349K
代理商: AD2S93AP
–5–
REV. A
AD2S93
GLOSSARY OF TERMS
INTEGRAL LINEARITY
Integral linearity deviation as a percent of full scale. A 0.1% de-
viation is equivalent to 8-LSB change on the output.
Gain
The converter gain is the maximum variation in the ratio of
A–B/REF/2 to the maximum digital input.
Output Offset
The output offset is the digital output code when the analog in-
put signal A–B = 0.
Overrange (OVR)
OVR goes high when A–B is in phase with REF and larger than
REF/2.
Underrange (UNR)
UNR goes high when A–B is out of phase with REF and larger
than REF/2.
PRINCIPLE OF OPERATION
The AD2S93 is based on a Type 2 tracking closed-loop prin-
ciple. The output tracks the position of the LVDT without the
need for external convert and wait states. As the transducer
moves through a position equivalent to the least significant bit
weighting, the output is updated by one LSB. On the AD2S93,
CLKOUT updates corresponding to one LSB increment. Fig-
ure 1 illustrates the principle of operation.
DEMODIN
CLKOUT
DEMOD OUT
ERROR
AMP
LOS
LATCHES
FREQUENCY
SHAPING
VCO
PHASE
SENSITIVE
DEMODULATOR
C1
C2
R2
VEL
VCO GAIN
UP-DOWN
COUNTER
REFERENCE
(PRIMARY
EXCITATION)
DIFFERENTIAL
(SECONDARY
VOLTAGE)
R4
REF
A
B
LOS
GAIN
V
DD
OVR
UNR
NULL
CS
DATA
SCLK
ACERROR
AC RATIO
BRIDGE
DIFF
DECODE
LOGIC
C3
AD2S93
INTIN
R3
SERIAL
INTERFACE
DIR
R5
R1
C4
R6
R7
Figure 1. Functional Block Diagram
Because the conversion depends on the ratio of the input signals
(ratiometric ac bridge), the AD2S93 is remarkably tolerant of
input amplitude and frequency. This, combined with the defin-
able Type 2 tracking closed-loop guarantees the AD2S93's re-
peatability for a given input. A phase sensitive detector,
integrator and voltage controlled oscillator (VCO) form a closed
loop system which seeks to null the output of the ACERROR.
When this is accomplished the word state of the up/down
counter equals within the rated accuracy of the converter, the
LVDT position output.
For more information on the operation of the converter, see
“Circuit Dynamics” section.
DATA FORMAT
OPERATING RANGE
The AD2S93 operating range is defined in Figure 2. The lin-
earity and specified operating range of the converter is the cen-
tral two 12-bit quadrants through zero. The corresponding
input relationship is –REF/2
A–B
+REF/2, (
±
is used to de-
note phase coherency). The sign bit is low for inputs with A–B
in phase with REF. The two remaining 12-bit quadrants are
used to denote over (OVR) and underrange (UNR). OVR goes
high when A–B is in phase with REF and larger than REF/2.
UNR goes high when A–B is out of phase with REF and larger
than REF/2. LOS is an open drain output which pulls high
when A and/or B are removed or REF is removed (see “Inbuilt
Diagnostics”), or A + B is less than 100 mV.
SCALING THE INPUTS
In order to match the LVDT output to the AD2S93 output, the
inputs to the AD2S93 need to be scaled. The operating range is
illustrated in Figure 2. The AD2S93 operates across
±
12-bit
range where the remaining 12-bit quadrants are used to denote
overrange and underrange. The output position word is a func-
tion of the ratio between A–B and V
REF
(see Figure 2) where:
±
FSR
=
(
A
B
)
V
REF
/2
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