
AD2S80A
REV. A
–8–
COMPONE NT SE LE CT ION
T he following instructions describe how to select the external
components for the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest “preferred
value” component should be used, and a 5% tolerance will not
degrade the overall performance of the converter. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. T he components should
be connected as shown in Figure 1.
PG compatible software is available to help users select the optimum
component values for the AD2S80A, and display the transfer gain,
phase and small step response.
For more detailed information and explanation, see section “CIR-
CUIT FUNCT IONS AND DYNAMIC PERFORMANCE.”
1. HF Filter (R1, R2, C1, C2)
T he function of the HF filter is to remove any dc offset and
to reduce the amount of noise present on the signal inputs to
the AD2S80A, reaching the Phase Sensitive Detector and af-
fecting the outputs. R1 and C2 may be omitted—in which
case R2 = R3 and C1 = C3, calculated below—but their use
is particularly recommended if noise from switch mode power
supplies and brushless motor drive is present.
Values should be chosen so that
15
k
≤
R
1
=
R
2
≤
56
k
C
1
=
C
2
1
2
π
R
1
f
REF
and f
REF
= Reference frequency
(Hz)
T his filter gives an attenuation of three times at the input to
the phase sensitive detector.
2. Gain Scaling Resistor (R4)
If R1, C2 arc fitted then:
R
4
=
E
DC
100
×
10
±9
×
1
3
where 100
×
10
–9
= current/LSB
If R1, C2 are not fitted then:
R
4
=
E
DC
100
×
10
±9
where E
DC
= 160
×
10
–3
for 10 bits resolution
= 40
×
10
–3
for 12 bits
= 10
×
10
–3
for 14 bits
= 2.5
×
10
–3
for 16 bits
= Scaling of the DC ERROR in volts
3. AC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. T hat is,
R
3
=
100
k
C
3
>
1
R
3
×
f
REF
F
with R3 in
.
4. Maximum T racking Rate (R6)
T he VCO input resistor R6 sets the maximum tracking rate
of the converter and hence the velocity scaling as at the max
tracking rate, the velocity output will be 8 V.
Decide on your maximum tracking rate, “T ,” in revolutions
per second. Note that “T ” must not exceed the maximum
tracking rate or 1/16 of the reference frequency.
R
6
=
6.32
×
10
10
T
×
n
where n = bits per revolution
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
5. Closed-Loop Bandwidth Selection (C4, C5, R5)
a. Choose the closed-loop bandwidth (f
BW
) required
ensuring that the ratio of reference frequency to band-
width does not exceed the following guidelines:
Resolution
Ratio of Reference Frequency/Bandwidth
10
12
14
16
7.5
T ypical values may be 100 Hz for a 400 Hz reference fre-
quency and 500 Hz to 1000 Hz for a 5 kHz reference
frequency.
b. Select C4 so that
2.5 : 1
4
6
: 1
: 1
: 1
C
4
=
21
R
6
×
f
BW
2
F
with R6 in
and f
BW
, in Hz selected above.
c. C5 is given by
C
5
=
5
×
C
4
d. R5 is given by
R
5
=
4
2
× π ×
f
BW
×
C
5
6. VCO Phase Compensation
T he following values of C6 and R7 should be fitted.
C
6
=
470
pF
,
R
7
=
68
7. Offset Adjust
Offsets and bias currents at the integrator input can cause an
additional positional offset at the output of the converter of 1
arc minute typical, 5.3 arc minutes maximum. If this can be
tolerated, then R8 and R9 can be omitted from the circuit.
If fitted, the following values of R8 and R9 should be used:
R
8
=
4.7
M
,
R
9
=
1
M
potentiometer
T o adjust the zero offset, ensure the resolver is disconnected
and all the external components are fitted. Connect the COS
pin to the REFERENCE INPUT and the SIN pin to the
SIGNAL GROUND and with the power and reference ap-
plied, adjust the potentiometer to give all “0s” on the digital
output bits.
T he potentiometer may be replaced with select on test resis-
tors if preferred.