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參數(shù)資料
| 型號： | AD2S80AKD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 位置變換器 |
| 英文描述： | Flat / Ribbon Cable |
| 中文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDIP40 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 268K |
| 代理商： | AD2S80AKD |
AD2S80A
REV. A
–9–
DAT A T RANSFE R
T o transfer data the
INHIBIT
input should be used. T he data
will be valid 600 ns after the application of a logic “LO” to the
INHIBIT
. T his is regardless of the time when the
INHIBIT
is
applied and allows time for an active BUSY to clear. By using
the
ENABLE
input the two bytes of data can be transferred af-
ter which the
INHIBIT
should be returned to a logic “HI” state
to enable the output latches to be updated.
BUSY Output
T he validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
T T L level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
INHIBIT
Input
T he
INHIBIT
logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT
automatically generates a BUSY pulse to refresh the
output data.
ENABLE
Input
T he
ENABLE
input determines the state of the output data. A
logic “HI” maintains the output data pins in the high imped-
ance condition, and the application of a logic “LO” presents the
data in the latches to the output pins. T he operation of the
ENABLE
has no effect on the conversion process.
BY T E SE LE CT Input
T he BYT E SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. T he least sig-
nificant byte will be presented on data output DB9 to DB16
(with the
ENABLE
input taken to a logic “LO”) regardless of
the state of the BYT E SELECT pin. Note that when the
AD2S80A is used with a resolution less than 16 bits the unused
data lines are pulled to a logic “LO.” A logic “HI” on the BYT E
SELECT input will present the eight most significant data bits
on data output DB1 and DB8. A logic “LO” will present the
least significant byte on data outputs 1 to 8, i.e., data outputs 1
to 8 will duplicate data outputs 9 to 16.
T he operation of the BYT E SELECT has no effect on the con-
version process of the converter.
RIPPLE CLOCK
As the output of the converter passes through the major carry,
i.e., all “1s” to all “0s” or the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
T he minimum pulse width of the ripple clock is 300 ns.
RIPPLE CLOCK is normally set high before a BUSY pulse and
resets before the next positive going edge of the next consecutive
pulse.
T he only exception to this is when DIR changes whist the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
If the AD2S80A is being used in a pitch and revolution count-
ing application, the ripple and busy will need to be gated to pre-
vent false decrement or increment (see Figure 2).
RIPPLE CLOCK is unaffected by
INHIBIT
.
IN4148
IN4148
RIPPLE
CLOCK
+5V
5k1
BUSY
+5V
10k
1k
2N3904
0V
TO COUNTER
(CLOCK)
NOTE: DO NOT USE ABOVE CCT WHEN
INHIBIT
IS "LO."
Figure 2. Diode Transistor Logic Nand Gate
DIRE CT ION Output
T he DIRECT ION (DIR) logic output indicates the direction of
the input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DAT A and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. T his corresponds to a change in input rotation
direction but less than 1 LSB.
DIGIT AL T IMING
t
2
t
4
t
5
t
7
t
8
t
10
t
1
t
3
t
9
BUSY
RIPPLE
CLOCK
DATA
DIR
DATA
BYTE
SELECT
DATA
INHIBIT
INHIBIT
ENABLE
t
6
V
H
V
L
V
H
V
H
V
L
V
H
V
H
V
L
V
L
V
L
t
11
V
H
V
Z
V
L
V
L
V
H
V
H
V
L
t
12
t
13
PARAMETER
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
T
MIN
200
10
470
16
3
70
485
515
–
40
35
60
60
T
MAX
600
25
580
45
25
140
625
670
600
110
110
140
125
CONDITION
BUSY WIDTH V
H
–V
H
RIPPLE CLOCK V
H
TO BUSY V
H
RIPPLE CLOCK V
L
TO NEXT BUSY V
H
BUSY V
H
TO DATA V
H
BUSY V
H
TO DATA V
L
INHIBIT
V
H
TO BUSY V
H
MIN DIR V
H
TO BUSY V
H
MIN DIR V
H
TO BUSY VH
INHIBIT
V
L
TO DATA STABLE
ENABLE
V
L
TO DATA V
H
ENABLE
V
L
TO DATA V
L
BYTE SELECT V
L
TO DATA STABLE
BYTE SELECT V
H
TO DATA STABLE
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