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參數(shù)資料
| 型號： | AD2S80AKD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 位置變換器 |
| 英文描述： | Flat / Ribbon Cable |
| 中文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDIP40 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 268K |
| 代理商： | AD2S80AKD |
AD2S80A
REV. A
–13–
VE LOCIT Y E RRORS
T he signal at the INT EGRAT OR OUT PUT pin relative to the
ANALOG GROUND pin is an analog voltage proportional to
the rate of change of the input angle. T his signal can be used to
stabilize servo loops or in the place of a velocity transducer. Al-
though the conversion loop of the AD2S80A includes a digital
section there is an additional analog feedback loop around the
velocity signal. T his ensures against flicker in the digital posi-
tional output in both dynamic and static states.
A better quality velocity signal will be achieved if the following
points are considered:
1. Protection.
T he velocity signal should be buffered before use.
2. Reversion error.
1
T he reversion error can be nulled by varying one supply rail
relative to the other.
3. Ripple and Noise.
Noise on the input signals to the converter is the major cause of
noise on the velocity signal.
T his can be reduced to a minimum
if the following precautions are taken:
T he resolver is connected to the converter using separate
twisted pair cable for the sine, cosine and reference signals.
Care is taken to reduce the external noise wherever possible.
An HF filter is fltted before the Phase Sensitive Demodulator
(as described in the section HF FILT ER).
A resolver is chosen that has low residual voltage, i.e., a small
signal in quadrature with the reference.
Components are selected to operate the AD2S80A with the
lowest acceptable bandwidth.
Feedthrough of the reference frequency should be removed by
a filter on the velocity signal.
Maintenance of the input signal voltages at 2 V rms will pre-
vent LSB flicker at the positional output. T he analog feed-
back or hysteresis employed around the VCO and the
intergrator is a function of the input signal levels (see section
“INT EGRAT OR”) .
Following the preceding precautions will allow the user to use
the velocity signal in very noisy environments, for example,
PWM motor drive applications. Resolver/converter error curves
may exhibit apparent acceleration/deceleration at a constant ve-
locity. T his results in ripple on the velocity signal of frequency
twice the input rotation.
1
Reversion error, or side-to-side nonlinearity, is a result of differences in the
up and down rates of the VCO.
SOURCE S OF E RRORS
Integrator Offset
Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator as it will
be treated as an error signal. T his error will typically be 1 arc
minute over the operating temperature range.
A description of how to adjust from zero offset is given in the
section “COMPONENT SELECT ION” and the circuit re-
quired is shown in Figure 1.
Differential Phase Shift
Phase shift between the sine and cosine signals from the resolver
is known as differential phase shift and can cause static error.
Some differential phase shift will be present on all resolvers as a
result of coupling. A small resolver residual voltage (quadrature
voltage) indicates a small differential phase shift. Additional phase
shift can be introduced if the sine channel wires and the cosine
channel wires are treated differently. For instance, different cable
lengths or different loads could cause differential phase shift .
T he additional error caused by differential phase shift on the in-
put signals approximates to
Error = 0.53 a
×
b arc minutes
where a = differential phase shift (degrees).
b = signal to reference phase shift (degrees).
T his error can be minimized by choosing a resolver with a small
residual voltage, ensuring that the sine and cosine signals are
handled identically and removing the reference phase shift (see
section “CONNECT ING T HE RESOLVER”). By taking these
precautions the extra error can be made insignificant.
Under static operating conditions phase shift between the refer-
ence and the signal lines alone will not theoretically affect the
converter’s static accuracy.
However, most resolvers exhibit a phase shift between the signal
and the reference. T his phase shift will give rise under dynamic
conditions to an additional error defined by:
Shaft Speed
(
rps
)
×
Phase Shift
(
Degrees
)
ReferenceFrequency
For example, for a phase shift of 20 degrees, a shaft rotation of
22 rps and a reference frequency of 5 kHz, the converter will ex-
hibit an additional error of:
22
×
20
5000
0.088
Degrees
T his effect can be eliminated by placing a phase shift in the ref-
erence to the converter equivalent to the phase shift in the re-
solver (see section “CONNECT ING T HE RESOLVER”).
Note: Capacitive and inductive crosstalk in the signal and reference
leads and wiring can cause similar problems.
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| AD2S80ALD | 功能描述:IC R/D CONV TRACKING 40CDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD2S80ASD | 功能描述:IC R/D CONV TRACKING 40CDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD2S80ASD/883B | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC - 多種 40 PIN DIP 8 ARC MIN 883B RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 分辨率:8 bit 工作電源電壓:2.7 V to 5.5 V 功耗: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:MSOP-10 封裝:Reel |
| AD2S80ASD883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Variable Resolution, Monolithic esolver-to-Digital Converter |
| AD2S80ASE | 制造商:AD 制造商全稱:Analog Devices 功能描述:Variable Resolution, Monolithic Resolver-to-Digital Converter |
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