參數(shù)資料
型號： AD2S105AP
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
中文描述： SPECIALTY ANALOG CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 8/12頁
文件大小： 292K
代理商： AD2S105AP
AD2S105
REV. 0
–8–
TIMING DIAGRAMS
Busy Output
The BUSY output will go HI at the negative edge of the
STROBE input. This is used to synchronize digital input data
and load the digital angular rotation information into the device
counter. The BUSY output will remain HI for 2
μ
s, and go LO
until the next strobe negative edge occurs.
Strobe Input
The width of the positive STROBE pulse should be at least
100 ns, in order to successfully start the conversion. The maxi-
mum frequency of STROBE input is 366 kHz, i.e., there should
be at least 2.73
μ
s from the negative edge of one STROBE pulse
to the next rising edge. This is illustrated by the following tim-
ing diagram and table.
t
1
t
2
t
3
t
4
STROBE
BUSY
t
f
t
r
Figure 7. AD2S105 Timing Diagram
Note: Digital data should be stable 25 ns before and after posi-
tive strobe edge.
Table II. AD2S105 Timing Table
Parameter
Min
Typ
Max
Condition
t
1
t
2
t
3
t
4
t
r
100 ns
STROBE Pulse Width
STROBE
↓
to BUSY
↑
BUSY Pulse Width
BUSY
↓
to STROBE
↑
BUSY Pulse Rise Time
with No Load
BUSY Pulse Rise Time
with 68 pF Load
BUSY Pulse Fall Time
with No Load
BUSY Pulse Fall Time
with 68 pF Load
30 ns
1.7
μ
s
2.5
μ
s
100 ns
20 ns
150 ns
t
f
10 ns
120 ns
TYPICAL CIRCUIT CONFIGURATION
Figure 8 shows a typical circuit configuration for the AD2S105
in a three phase, nominal level input mode (MODE2).
T
AD2S105
TOP VIEW
1
41
38
30
27
23
12
PH/IP3
16
PH/IP1
D
LSB
S
C
10
μ
F
100nF
10
μ
F
100nF
–5V
+5V
GND
T
S
B
H
H
H
MSB
PH/OP1
AGND
PH/IP4
PH/IP2
34
Figure 8. Typical Circuit Configuration
APPLICATIONS
Transformation Configuration
The AD2S105 can perform both forward and reverse transfor-
mations. The section “Theory of Operation” explains how the
chip operates with the core operator e
+j
f
, which performs a for-
ward transformation. The reverse transformation, e
–j
f
, is per-
formed by providing a negative angle
φ
. Figure 9 shows two
different phase input/output connections for AD2S105 reverse
transformation operation.
FORWARD
TRANSFORMATION
AD2S105
REVERSE
TRANSFORMATION
AD2S105
e
+j
φ
2 PHASE – 2 PHASE
Sin
θ
Cos
θ
Cos(
θ
+
φ
)
Sin(
θ
+
φ
)
Cos
θ
Sin
θ
Cos(
θ
–
φ
)
Sin(
θ
–
φ
)
e
–j
φ
–1
e
+j
φ
3 PHASE – 2 PHASE
Cos
θ
Cos(
θ
+ 120
°
)
Cos(
θ
+ 240
°
)
Cos(
θ
+
φ
)
Sin(
θ
+
φ
)
Cos
θ
Cos(
θ
+ 120
°
)
Cos(
θ
+ 240
°
)
Cos(
θ
–
φ
)
Sin(
θ
–
φ
)
e
–j
φ
Figure 9. Forward and Reverse Transformation Connections
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