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參數(shù)資料
| 型號： | AD1981BL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | AC ’97 SoundMAX㈢ Codec |
| 中文描述： | ㈢交流\u0026#39;97 SoundMAX編解碼器 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大小： | 215K |
| 代理商： | AD1981BL |
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REV. 0
–4–
AD1981BL
SPECIFICATIONS
(continued)
Parameter
Set Bits
DV
DD
Typ
AV
DD
Typ
Unit
POWER-DOWN STATES
*
(Fully Active)
ADC
DAC
ADC + DAC
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Standby
Headphone Standby
(No Bits Value)
PR0
PR1
PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
PR5, PR4, PR3, PR2, PR1, PR0
PR6
47.76
40.1
32.8
13.2
47.7
40
32.77
13.9
0
47.7
38.9
34.39
26.3
20.55
19.39
14.86
6.39
1.15
0
32
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*
Values presented with V
REFOUT
not loaded.
Specifications subject to change without notice.
TIMING PARAMETERS
(Guaranteed over Operating Temperature Range)
Parameter
Symbol
Min
Typ
Max
Unit
RESET
Active Low Pulse Width
RESET
Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulse Width
SYNC Low Pulse Width
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Period
BIT_CLK Output Jitter
1, 2, 3
BIT_CLK High Pulse Width
BIT_CLK Low Pulse Width
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET
(Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to Hi-Z Delay
Propagation Delay
RESET
Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
t
RST_LOW
t
RST2CLK
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC2CLK
1.0
ms
ns
μ
s
μ
s
ns
MHz
ppm
ns
ps
ns
ns
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
162.8
1.3
19.5
162.8
12.288
±
1
t
CLK_PERIOD
81.4
750
42
38
48.0
20.8
2.5
2000
48.84
t
CLK_HIGH
t
CLK_LOW
32.56
32.56
t
SYNC_PERIOD
t
SETUP
t
HOLD
t
RISECLK
t
FALLCLK
t
RISESYNC
t
FALLSYNC
t
RISEDIN
t
FALLDIN
t
RISEDOUT
t
FALLDOUT
t
S2_PDOWN
5
5
2
2
2
2
2
2
2
2
0
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
1.0
t
SETUP2RST
t
OFF
15
ns
ns
ns
ns
ns
25
15
50
15
NOTES
1
Guaranteed but not tested.
2
Output jitter is directly dependent on crystal input jitter.
3
Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower.
Specifications subject to change without notice.
Parameter
CLOCK SPECIFICATIONS
1
Input Clock Frequency
Recommended Clock Duty Cycle
Min
Typ
Max
Unit
24.576
50
MHz
%
40
60
NOTES
1
Guaranteed but not tested.
2
Measurements reflect main ADC.
Specifications subject to change without notice.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1981BLJSTZ2 | AC ’97 SoundMAX㈢ Codec |
| AD1981BLJSTZ-REEL2 | AC ’97 SoundMAX㈢ Codec |
| AD1981HD | HD Audio SoundMAX Codec |
| AD1981HDJSTZ | HD Audio SoundMAX Codec |
| AD1981HDJSTZ-REEL | HD Audio SoundMAX Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1981BLJST | 制造商:Analog Devices 功能描述: |
| AD1981BLJST-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX㈢ Codec |
| AD1981BLJSTZ | 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD1981BLJSTZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX㈢ Codec |
| AD1981BLJSTZ-REEL | 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP T/R |
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