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參數(shù)資料
| 型號： | AD1981BL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | AC ’97 SoundMAX㈢ Codec |
| 中文描述： | ㈢交流\u0026#39;97 SoundMAX編解碼器 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大小： | 215K |
| 代理商： | AD1981BL |
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REV. 0
AD1981BL
–19–
VRA
Variable Rate Audio (Read/Write).
VRA = 0 sets fixed sample rate audio at 48 kHz (reset default).
VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling).
SPDIF
SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write).
SPDIF = 1 enables the SPDIF transmitter.
SPDIF = 0 disables the SPDIF transmitter (default).
This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is allowed
to be set high only if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the
SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low,
indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF
transmitter is actually enabled.
SPSA[1:0]
SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults,
depending on the codec ID configuration.
SPCV
SPDIF Configuration Valid (Read-Only). Indicates the status of the SPDIF transmitter subsystem, enabling the
driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent
of the SPDIF enable bit status.
SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).
SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported).
VFORCE
Validity Force Bit (Reset Default = 0).
When asserted, this bit forces the SPDIF stream Validity flag (Bit 28 within each SPDIF L/R subframe) to be
controlled by the V bit (D15) in Register 3Ah (SPDIF control register).
VFORCE = 0 and V = 0; the Validity bit is managed by the codec error detection logic.
VFORCE = 0 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.
VFORCE = 1 and V = 0; the Validity bit is forced low, indicating subframe data is valid.
VFORCE = 1 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.
Extended Audio Status and Control Register (Index 2Ah)
Reg
No. Name
D15
D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1 D0
Default
2Ah Ext’d Audio Stat/Ctrl VFORCE
X
X
X
X
SPCV
X
X
X
X
SPSA1
SPSA0
X
SPDIF X
VRA
0000h
All registers not shown and bits containing an X are assumed to be reserved. The Extended Audio Status and Control register is a read/write register that provides
status and control of the extended audio features.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1981BLJSTZ2 | AC ’97 SoundMAX㈢ Codec |
| AD1981BLJSTZ-REEL2 | AC ’97 SoundMAX㈢ Codec |
| AD1981HD | HD Audio SoundMAX Codec |
| AD1981HDJSTZ | HD Audio SoundMAX Codec |
| AD1981HDJSTZ-REEL | HD Audio SoundMAX Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1981BLJST | 制造商:Analog Devices 功能描述: |
| AD1981BLJST-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX㈢ Codec |
| AD1981BLJSTZ | 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD1981BLJSTZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX㈢ Codec |
| AD1981BLJSTZ-REEL | 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP T/R |
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