參數(shù)資料
型號(hào)： AD1981BL
廠(chǎng)商： Analog Devices, Inc.
元件分類(lèi)： Codec
英文描述： AC ’97 SoundMAX㈢ Codec
中文描述： ㈢交流\u0026#39;97 SoundMAX編解碼器
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 215K
代理商： AD1981BL
REV. 0
AD1981BL
–26–
SPLNK
SPDIF Link. This bit enables the SPDIF to link with the DAC for data requesting.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
SPDZ
SPDIF DACZ.
0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO underruns.
SPAL
SPDIF ADC Loop-Around.
0 = SPDIF transmitter is connected to the ac-link stream (reset default).
1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link.
INTS
Interrupt Mode Select. This bit selects the JS interrupt implementation path.
0 = Bit 0 SLOT 12 (modem interrupt).
1 = Slot 6 valid bit (MIC ADC interrupt).
CHEN
Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
REGM0
Master Codec Register Mask.
REGM1
Slave 1 Codec Register Mask.
REGM2
Slave 2 Codec Register Mask.
SLOT16
Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a
preferred mode for DSP serial port interfacing.
MBG[1:0]
MIC Boost Gain Change Register.
These two bits allow changing the MIC preamp gain from the nominal 20 dB gain.
Note: This gain setting takes affect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise,
the MIC boost block has a gain of 0 dB.
00 = 20 dB gain (reset default).
01 = 10 dB gain.
10 = 30 dB gain.
11 = Reserved.
VREFD
V
REFOUT
Disable. Disables V
REFOUT
, placing it into High Z Out mode. Note that this bit overrides the VREFH bit
selection (see below).
0 = V
REFOUT
pin is driven by the internal reference (reset default).
1 = V
REFOUT
pin is placed into High Z Out mode.
V
REFOUT
High. Changes V
REFOUT
from 2.25 V to 3.70 V for MIC bias applications.
0 = V
REFOUT
pin is set to 2.25 V output (reset default).
1 = V
REFOUT
pin is set to 2.25 V output.
VREFH
Serial Configuration Register (Index 74h)
Reg
No. Name D15
D14
D13
D12
D11 D10 D9 D8
D7 D6 D5 D4
D3 D2
D1
D0
Default
74h Serial
Config-
uration
SLOT16 REGM2 REGM1 REGM0 X
X
X
CHEN X
X
X
INTS X
SPAL SPDZ SPLNK 7001h
This register is not reset when the reset register (Register 00h) is written. All registers not shown and bits containing an X are assumed to be reserved.
Miscellaneous Control Bit Register (Index 76h)
Reg
No.
Name
D15
D14 D13
D12
D11
D10 D9
D8 D7
D6
D5 D4
D3
D2
D1
D0
Default
76th Misc
DACZ X
MSPLT LODIS DAM X
FMXE X
MADPD 2CMIC X
MADST VREFH VREFD MBG1 MBG0 0000h
Control Bits
All registers not shown and bits containing an X are assumed to be reserved.
相關(guān)PDF資料
PDF描述
AD1981BLJSTZ2 AC ’97 SoundMAX㈢ Codec
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1981BLJST 制造商:Analog Devices 功能描述:
AD1981BLJST-REEL 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:AC ’97 SoundMAX㈢ Codec
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AD1981BLJSTZ2 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:AC ’97 SoundMAX㈢ Codec
AD1981BLJSTZ-REEL 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP T/R
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