參數(shù)資料
型號: AD1933YSTZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 4/28頁
文件大?。?/td> 0K
描述: IC DAC 24BIT SRL/SPI 8CH
標準包裝: 1,500
位數(shù): 24
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 模擬和數(shù)字
功率耗散(最大): 429mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 8 電壓,雙極
采樣率(每秒): 192k
AD1933
Data Sheet
Rev. E | Page 12 of 28
SERIAL CONTROL PORT
The AD1933 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. A standalone mode is also available
for operation without serial control; standalone is configured
at reset by connecting CIN, CCLK, and CLATCH to ground.
In standalone mode, all registers are set to default, except the
internal MCLK enable, which is set to 1. The ADC ABCLK and
ALRCLK clock ports are set to master/slave by the connecting
the COUT pin to either DVDD or ground. Standalone mode
only supports stereo mode with an I2S data format and 256 fS
MCLK rate. Refer to Table 11 for details. If CIN, CCLK, and
CLATCH are not grounded, the AD1933 SPI port is active. It
is recommended to use a weak pull-up resistor on CLATCH in
applications that have a microcontroller. This pull-up resistor
ensures that the AD1933 recognizes the presence of a micro-
controller.
The SPI control port of the AD1933 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
DACs. Figure 9 shows the format of the SPI signal. The first
byte is a global address with a read/write bit. For the AD1933,
the address is 0x04, shifted left 1 bit due to the R/W bit. The
second byte is the AD1933 register address and the third byte
is the data.
D0
D8
D22
D23
D9
CLATCH
CCLK
CIN
COUT
tCCH tCCL
tCDS tCDH
tCLS
tCCP
tCLH
tCOTS
tCOD
tCOE
0
662
4-
0
09
Figure 9. Format of SPI Signal
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