參數(shù)資料
型號(hào): AD1933YSTZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 11/28頁(yè)
文件大?。?/td> 0K
描述: IC DAC 24BIT SRL/SPI 8CH
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 24
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 模擬和數(shù)字
功率耗散(最大): 429mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 8 電壓,雙極
采樣率(每秒): 192k
Data Sheet
AD1933
Rev. E | Page 19 of 28
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1933 is 0x04, shifted left 1 bit due to the R/W bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 13. Register Format
Global Address
R/W
Register Address
Data
Bit
23:17
16
15:8
7:0
Table 14. Register Addresses and Functions
Address
Function
0
PLL and Clock Control 0
1
PLL and Clock Control 1
2
DAC Control 0
3
DAC Control 1
4
DAC Control 2
5
DAC individual channel mutes
6
DAC L1 volume control
7
DAC R1 volume control
8
DAC L2 volume control
9
DAC R2 volume control
10
DAC L3 volume control
11
DAC R3 volume control
12
DAC L4 volume control
13
DAC R4 volume control
14
Reserved
15
Auxiliary TDM Port Control 0
16
Auxiliary TDM Port Control 1
PLL AND CLOCK CONTROL REGISTERS
Table 15. PLL and Clock Control 0
Bit
Value
Function
Description
0
Normal operation
PLL power-down
1
Power-down
2:1
00
Input 256 (×44.1 kHz or 48 kHz)
MCLKI/XI pin functionality (PLL active), master clock rate setting
01
Input 384 (×44.1 kHz or 48 kHz)
10
Input 512 (×44.1 kHz or 48 kHz)
11
Input 768 (×44.1 kHz or 48 kHz)
4:3
00
XTAL oscillator enabled
MCLKO/XO pin, master clock rate setting
01
256 × fS VCO output
10
512 × fS VCO output
11
Off
6:5
00
MCLKI/XI
PLL input
01
DLRCLK
10
AUXTDMLRCLK
11
Reserved
7
0
Disable: DAC idle
Internal master clock enable
1
Enable: DAC active
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