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參數(shù)資料
| 型號： | AD1888JST-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CONNECTOR |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 312K |
| 代理商： | AD1888JST-REEL |
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REV. 0
AD1888
–19–
Extended Audio Status and Control Register (Index 2Ah)
Reg
No. Name
D15
D14 D13 D12 D11 D10
D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
2Ah Extended Audio VFORCE X
Stat/Ctrl
PRK PRJ
PRI SPCV X
ELDAC ESDAC ECDAC SPSA1 SPSA0 X
ESPDIF EDRA EVRA 0xx0h
The extended audio status and control register is a read/write register that provides status and control of the extended audio features. All registers not shown and bits
containing an X are assumed to be reserved.
EVRA
Variable Rate Audio (Read/Write).
EVRA = 0, sets fixed sample rate audio at 48 kHz (Reset Default).
EVRA = 1, enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling).
EDRA
Double Rate Audio.
EDRA = 1 enables double rate audio mode in which data from PCM L and PCM R in output slots 3 and 4 is used
in conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate
designated by the PCM front sample rate control register. When using the double rate audio, only the front DACs
are supported and all other DACs (surround, center, and LFE) are automatically powered down.
Note that EDRA can be used without VRA; in that case, the converter rates are forced to 96 kHz if EDRA = 1.
ESPDIF
SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write).
ESPDIF = 1 enables the SPDIF transmitter.
ESPDIF = 0 disables the SPDIF transmitter (default).
SPSA[1,0]
SPDIF Slot Assignment Bits (Read/Write).
These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration.
See the following table.
ECDAC
Center DAC Status (Read Only).
ECDAC = 1 indicates the PCM center DAC is ready.
ESDAC
Surround DAC status (Read Only).
ESDAC = 1 indicates the PCM surround DACs are ready.
ELDAC
LFE DAC status (Read Only).
ELDAC = 1 indicates the PCM LFE DAC is ready.
SPCV
SPDIF Configuration Valid (Read Only). Indicates the status of the SPDIF transmitter subsystem, enabling the
driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, indepen-
dent of the SPDIF enable bit status.
SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).
SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (supported).
PRI
Center DAC Power-Down (Read/Write).
PRI = 1 turns off the PCM Center DAC.
PRJ
Surround DACs Power-Down (Read/Write).
PRJ = 1 turns off the PCM surround DACs.
PRK
LFE DAC Power-Down (Read/Write).
PRK = 1 turns off the PCM LFE DAC.
VFORCE
Validity Force Bit (Reset Default = 0).
When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be con-
trolled by the V bit (D15) in Register 3Ah (SPDIF control register).
VFORCE = 0 and V = 0; the Validity Bit is managed by the codec error detection logic.
VFORCE = 0 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid.
VFORCE = 1 and V = 0; the Validity Bit is forced low, indicating subframe data is valid.
VFORCE = 1 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid.
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PDF描述 |
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| AD1888JSTZ | CONNECTOR COAXIAL BNC |
| AD1888JSTZ-REEL | CONNECTOR COAXIAL BNC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1888JSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec |
| AD1888JSTZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec |
| AD1889JS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1890 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SamplePort Stereo Asynchronous Sample Rate Converters |
| AD1890JN | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W 制造商:Rochester Electronics LLC 功能描述:IC, 20-BIT CONVERTER IC - Bulk |
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