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參數(shù)資料
| 型號： | AD1888JST-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CONNECTOR |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 10/32頁 |
| 文件大小： | 312K |
| 代理商： | AD1888JST-REEL |
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REV. 0
–10–
AD1888
Master Volume Register (Index 02h)
Reg
No.
Name
D15
D14 D13
1
D12
D11
D10
D9
D8
D7
D6 D5
1
D4
D3
D2
D1
D0
Default
02h
Master
Volume
MM
X
LMV5
LMV4
LMV3
LMV2
LMV1 LMV0 MMRM
2
X
RMV5 RMV4 RMV3 RMV2
RMV1 RMV0 8000h
NOTES
1
Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and mute bit. Each volume subregister contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are
set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.
2
For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality:
For AC97NC = 0, the register controls the Line_out output Attenuators only.
For AC97NC = 1, the register controls the Line_out, Center, and LFE output Attenuators.
Reset Register (Index 00h)
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0090h
NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1888 based on the following:
Bit = 1
Function
AD1888
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Dedicated Mic PCM In Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
0
0
0
0
1
0
0
1
0
0
SE[4:0] Stereo Enhancement. The AD1888 does not provide hardware 3D stereo enhancement. (All bits are zeros.)
RMV[5:0]
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of 46.5 dB.
MMRM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the MM bit. Otherwise this bit will always read 0 and will have no effect when set to 1.
LMV[5:0]
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB
to a maximum attenuation of 46.5 dB.
MM
Headphones Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the
MSPLT bit in Register 76h is set to 1.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD1888JSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec |
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