參數(shù)資料
型號(hào): AD1871YRSZ
廠商: Analog Devices Inc
文件頁數(shù): 3/28頁
文件大?。?/td> 0K
描述: IC ADC STEREO AUDIO 24BIT 28SSOP
產(chǎn)品培訓(xùn)模塊: Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝: 47
位數(shù): 24
采樣率(每秒): 96k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
輸入數(shù)目和類型: 4 個(gè)單端,單極
產(chǎn)品目錄頁面: 777 (CN2011-ZH PDF)
REV. 0
AD1871
–11–
Pin Function Redefinition in External Control Mode
Pin
Input/
No.
Output
Mnemonic
Description
2I
256/512
Clock Rate Select. This pin is used to select between an MCLK of 256
fS (pin low) or
512
fS (pin high).
3I
DF0
Data Format Select 0. This pin is used as the low bit (DF0) of the data format selection
(see section on External Control).
4I
DF1
Data Format Select 1. This pin is used as the high bit (DF1) of the data format selection
(see section on External Control).
5I
M/S
Master/Slave Select. This pin is used to select between the Master (pin low) or Slave (pin
high) Modes.
Pin Function Redefinition in Modulator Mode
Pin
Input/
No.
Output
Mnemonic
Description
3O
MODCLK
This pin provides a clock output that allows the user to decode the left and right channel
modulator outputs. It is similar to a left/right clock but runs (nominally) at 5.6448 MHz
and gates a 4-bit modulator output word in each phase (see section on Modulator Mode).
25
O
D3
Bit 3 of the Modulator Output Word
26
O
D2
Bit 2 of the Modulator Output Word
27
O
D1
Bit 1 of the Modulator Output Word
28
O
D0
Bit 0 of the Modulator Output Word
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參數(shù)描述
AD1871YRSZ 制造商:Analog Devices 功能描述:IC, ADC, 24BIT, 96KHZ, SSOP-28
AD1871YRSZ-REEL 功能描述:IC ADC STEREO 24BIT 96KHZ 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率(每秒):45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散(最大):315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC(0.295",7.50mm 寬) 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端,單極
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