參數(shù)資料
型號(hào): AD1837AAS
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP52
封裝: PLASTIC, MS-022AC, MQFP-52
文件頁(yè)數(shù): 21/24頁(yè)
文件大小: 401K
代理商: AD1837AAS
REV. A
AD1837A
–21–
Table IX. ADC Peak
Function
Four
Fixed Bits
Address
R/
W
RES
Six Data Bits
15, 14, 13, 12
11
10
9, 8, 7, 6, 5, 4
3, 2, 1, 0
1010 = Left ADC
1011 = Right ADC
1
0
000000 = 0 dBFS
000001 = –1 dBFS
000010 = –2 dBFS
0000
These
four bits
are always
zero.
111111 = –63 dBFS
Table X. ADC Control 1
Function
ADC
Power-Down
Sample
Rate
Address
R/
W
RES
Reserved
Filter
Reserved
15, 14, 13, 12
1100
11
0
10
0
9
0
8
0 = All Pass
1 = High-Pass
7
0 = Normal
1 = Power-Down
6
0 = 48 kHz
1 = 96 kHz
5, 4, 3, 2, 1, 0
0, 0, 0, 0, 0, 0
0, 0, 0, 0, 0, 0
Table XI. ADC Control 2
Function
R/
W
RES
Master/Slave
Aux Mode
ADC
Data Format
ADC Data-
Word Width
ADC MUTE
Right
Address
RES
Reserved
Left
15, 14, 13, 12
1101
11
0
10
0
9
0 = Slave
1 = Master
8, 7, 6
000 = I
2
S
001 = RJ
010 = DSP
011 = LJ
100 = Packed 256
101 = Packed 128
110 = Auxiliary 256
111 = Auxiliary 512
5, 4
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
3, 2
0, 0
1
0 = On
1 = Mute
0
0 = On
1 = Mute
Table XII. ADC Control 3
Function
R/
W
RES
IMCLK
Clocking Scaling
ADC
Peak Readback
DAC
Test Mode
ADC
Test Mode
Address
RES
Reserved
15, 14,
13, 12
1110
11
0
10
0
9, 8
0, 0
7, 6
00 = MCLK 2
01 = MCLK
10 = MCLK
2/3
11 = MCLK
2
5
0 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode
1 = Enabled Peak Readback
All others reserved
4, 3, 2
1, 0
All others reserved
Table VIII. DAC Volume Control
Function
DAC Volume
Address
R/
W
RES
15, 14, 13, 12
11
10
9, 8, 7, 6, 5, 4, 3, 2, 1, 0
0010 = DACL1
0011 = DACR1
0100 = DACL2
0101 = DACR2
0110 = DACL3
0111 = DACR3
1000 = DACL4
1001 = DACR4
0
0
0000000000 = Mute
0000000001 = 1/1023
0000000010 = 2/1023
1111111110 = 1022/1023
1111111111 = 1023/1023
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