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REV. 0
AD1833
–5–
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
IN/OUT
Description
1
2
3, 4, 33, 34, 44
5, 6, 7, 30, 31, 32, 41
8, 29
9
10
11
12
13
14
15
16
17
18
19
20
OUTLP1
OUTLN1
AVDD
AGND
DGND
DVDD1
ZEROA
ZERO3R
ZERO3L
ZERO2R
CLATCH
CDATA
CCLK
L/
R
CLK
BCLK
MCLK
SDIN1
O
O
DAC 1 Left Channel Positive Output.
DAC 1 Left Channel Negative Output.
Analog Supply.
Analog Ground.
Digital Ground.
Digital Supply to Core Logic.
Flag to Indicate Zero Input on All Channels.
Flag to Indicate Zero Input on Channel 3 Right.
Flag to Indicate Zero Input on Channel 3 Left.
Flag to Indicate Zero Input on Channel 2 Right.
Latch Input for Control Data (SPI Port).
Serial Control Data Input (SPI Port).
Clock Input for Control Data (SPI Port).
Left/Right Clock for DAC Data Input (FSTDM Output in TDM Mode).
Bit Clock for DAC Data Input (BCLKTDM Output in TDM Mode).
Master Clock Input.
Data Input for Channel 1 Left/Right (Data Stream Input in TDM
and Packed Modes).
Data Input for Channel 2 Left/Right (L/
R
CLK Output to Auxiliary
DAC in TDM Mode).
Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary
DAC in TDM Mode).
Auxiliary I
2
S Output (Available in TDM Mode).
Flag to Indicate Zero Input on Channel 2 Left.
Flag to Indicate Zero Input on Channel 1 Right.
Flag to Indicate Zero Input on Channel 1 Left.
Power-Down and Reset Control.
Power Supply to External Interface Logic.
DAC 1 Right Channel Negative Output.
DAC 1 Right Channel Positive Output.
DAC 2 Right Channel Negative Output.
DAC 2 Right Channel Positive Output.
DAC 3 Right Channel Negative Output.
DAC 3 Right Channel Positive Output.
Reference/Filter Capacitor Connection. Recommend 10
μ
F/100
μ
F
Decouple to Analog Ground.
Filter Capacitor Connection. Recommend 10
μ
F/100
μ
F Decouple to
Analog Ground.
DAC 3 Left Channel Positive Output.
DAC 3 Left Channel Negative Output.
DAC 2 Left Channel Positive Output.
DAC 2 Left Channel Negative Output.
O
O
O
O
I
I
I
I/O
I/O
I
I
21
SDIN2
I/O
22
SDIN3
I/O
23
24
25
26
27
28
35
36
37
38
39
40
42
SOUT
ZERO2L
ZERO1R
ZERO1L
RESET
DVDD2
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
OUTRP3
FILTR
O
O
O
O
I
O
O
O
O
O
O
43
FILTD
45
46
47
48
OUTLP3
OUTLN3
OUTLP2
OUTLN2
O
O
O
O
D15
D14
D0
t
CHD
t
CCH
t
CSU
t
CCL
CDATA
CCLK
CLATCH
t
CLH
Figure 3. SPI Timing