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參數(shù)資料
| 型號： | AD1833AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multichannel 24-Bit, 192 kHz, DAC |
| 中文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 419K |
| 代理商： | AD1833AST |
REV. 0
AD1833
–12–
I
2
S Timing
I
2
S timing uses an L/
R
CLK to define when the data being trans-
mitted is for the left channel and when it is for the right channel.
The L/
R
CLK is low for the left channel and high for the right
channel. A bit clock running at 64
×
f
S
is used to clock in the
data. There is a delay of one bit clock from the time the L/
R
CLK
signal changes state to the first bit of data on the SDINx lines.
The data is written MSB first and is valid on the rising edge of
bit clock.
Left Justified Timing
Left Justified (LJ) timing uses an L/
R
CLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
R
CLK is high for the left channel and
low for the right channel. A bit clock running at 64
×
f
S
is used
to clock in the data. The first bit of data appears on the SDINx
lines at the same time the L/
R
CLK toggles. The data is written
MSB first and is valid on the rising edge of bit clock.
Right Justified Timing
Right Justified (RJ) timing uses an L/
R
CLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
R
CLK is high for the left channel and
low for the right channel. A bit clock running at 64
×
f
S
is used
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/
R
CLK toggles. In RJ
mode the LSB of data is always clocked by the last bit clock
before L/
R
CLK transitions. The data is written MSB first and
is valid on the rising edge of bit clock.
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
MSB
L/
R
CLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–
2
–
1
MSB
+1
LSB
+2
–
2
–
1
MSB
Figure 4. I
2
S Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
L/
R
CLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–
2
–
1
MSB
+1
LSB
+2
–
2
–
1
MSB
–
1
MSB
Figure 5. Left-Justified Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
L/
R
CLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–
2
–
1
LSB
MSB
+1
LSB
+2
–
2
–
1
MSB
Figure 6. Right-Justified Timing Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1833AST-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1833CST | 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1833CST-REEL | 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1835 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| AD1835A | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs |
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