參數(shù)資料
型號(hào)： AD1833AST
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Multichannel 24-Bit, 192 kHz, DAC
中文描述： SERIAL INPUT LOADING, 24-BIT DAC, PQFP48
封裝： PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 11/20頁(yè)
文件大小： 419K
代理商： AD1833AST
REV. 0
AD1833
–11–
MCLK Select
The AD1833 allows the matching of available external MCLK
frequencies to the required sample rate. The oversampling rate
can be selected from 256
×
f
S
, 512
×
f
S
or 768
×
f
S
by writing to
Bit 4 and Bit 3. Internally the AD1833 requires an MCLK of
512
×
f
S
; therefore, in the case of 256
×
f
S
mode, a clock doubler
is used, whereas in 768
×
f
S
mode, a divide-by-3 block (/3) is
first implemented, followed by a clock doubler. See Table XII.
Table XII. MCLK Settings
Bit 4
Bit 3
Oversample Ratio
256
×
f
S
(MCLK
×
2 Internally)
512
×
f
S
768
×
f
S
(MCLK
×
2/3 Internally)
Reserved
0
0
1
1
0
1
0
1
Channel Zero Status
The AD1833 provides individual logic output status indicators
when zero data is sent to a channel for 1024 or more consecutive
sample periods. There is also a global zero flag that indicates all
channels contain zero data. The polarity of the active zero signal
Table XIV. MCLK vs. Sample Rate Selection
MCLK (MHz)
256 f
S
Sampling Rate f
S
(kHz)
32
64
128
Interpolator Mode
8
×
(Normal)
4
×
(Double)
2
×
(4 Times)
8
×
(Normal)
4
×
(Double)
2
×
(4 Times)
8
×
(Normal)
4
×
(Double)
2
×
(4 Times)
512 f
S
768 f
S
8.192
16.384
24.576
44.1
88.2
176.4
11.2896
22.5792
33.8688
48
96
192
12.288
24.576
36.864
Table XV. Volume Control Registers
Address
Reserved
*
Volume Control
15–12
11
10
9–0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
Channel 1 Volume Control (OUTL1)
Channel 2 Volume Control (OUTR1)
Channel 3 Volume Control (OUTL2)
Channel 4 Volume Control (OUTR2)
Channel 5 Volume Control (OUTL3)
Channel 6 Volume Control (OUTR3)
*
Must be programmed to zero.
is programmable by writing to Control Bit 2, see Table XIII.
The six individual channel flags are best used as three stereo
zero flags by combining pairs of them through suitable logic
gates. Then, when both the left and right input are zero for 1024
clock cycles, i.e., a stereo zero input for 1024 sample periods,
the combined result of the two individual flags will go active
indicating a stereo zero.
Table XIII. Zero Detect
Bit 2
Channel Zero Status
0
1
Active High
Active Low
DAC Volume Control Registers
The AD1833 has six volume control registers, one each for the
six DAC channels. Volume control is exercised by writing to the
relevant register associated with each DAC. This setting is used
to attenuate the DAC output. Full-scale setting (all 1s) is equiva-
lent to zero attenuation. See Table XV.
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參數(shù)描述
AD1833AST-REEL 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
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AD1835 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
AD1835A 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs
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