參數(shù)資料
型號(hào)： AD1819
廠商： Analog Devices, Inc.
英文描述： ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
中文描述： AC\u0026#39;97音效SoundPort編解碼器
文件頁(yè)數(shù)： 6/28頁(yè)
文件大?。?/td> 245K
代理商： AD1819
AD1819B
–6–
REV. 0
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
RESET
Active Low Pulsewidth
RESET
Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to
SYNC, SDATA_OUT)
Rising Edge of
RESET
to HI-Z Delay
Symbol
t
RST_LOW
t
RST2CLK
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC2CLK
Min
1.0
162.8
0.0814
Typ
Max
Units
μ
s
ns
μ
s
μ
s
ns
MHz
ns
ps
ns
ns
kHz
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
1.3
19.5
162.8
12.288
81.4
t
CLK_PERIOD
750
48.84
48.84
t
CLK_HIGH
t
CLK_LOW
32.56
32.56
40.7
40.7
48.0
20.8
t
SYNC_PERIOD
t
SETUP
t
HOLD
t
RISE CLK
t
FALL CLK
t
RISE SYNC
t
FALL SYNC
t
RISE DIN
t
FALL DIN
t
RISE DOUT
t
FALL DOUT
t
S2_PDOWN
15.0
15.0
4
4
4
4
4
4
4
4
1.0
t
SETUP2RST
t
OFF
15
ns
ns
25
*Output Jitter is directly dependent on crystal input jitter.
RESET
BIT_CLK
t
RST2CLK
t
RST_LOW
Figure 1. Cold Reset
SYNC
BIT_CLK
t
SYNC_HIGH
t
RST2CLK
Figure 2. Warm Reset
t
CLK_HIGH
BIT_CLK
t
CLK_LOW
SYNC
t
SYNC_HIGH
t
SYNC_PERIOD
t
SYNC_LOW
t
CLK_PERIOD
Figure 3. Clock Timing
相關(guān)PDF資料
PDF描述
AD1819B AC’97 SoundPort Codec
AD1833A 24-Bit, 192 kHz, DAC
AD1833AAST ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1833ACST ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD1833ACST-REEL 24-Bit, 192 kHz, DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1819AJST 制造商:Rochester Electronics LLC 功能描述:
AD1819B 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec
AD1819BJST 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 48-Pin LQFP 制造商:Analog Devices 功能描述:IC CODEC AC'97 VERSION 2.1
AD1819BJST-REEL 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 48-Pin LQFP T/R
AD1819BJSTZ 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 48-Pin LQFP 制造商:Analog Devices 功能描述:Audio CODEC IC
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