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參數(shù)資料
| 型號： | ACT-7000ASC-225F24Q |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 225 MHz, RISC PROCESSOR, CQFP208 |
| 封裝： | 1.120 X 1.120 INCH, INVERTED, CERAMIC, QFP-208 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 231K |
| 代理商： | ACT-7000ASC-225F24Q |
14
SCD7000A Rev C 9/9/09
Aeroflex Plainview
Performance Counters
Like the Test/Break-point capability described above,
the Performance Counter feature has been added to
improve the observability and controllability of the
processor thereby easing system debug and, especially in
the case of the performance counters, easing system tuning.
The Performance Counter feature is implemented using
two new CP0 registers, PerfCount and PerfControl. The
PerfCount register is a 32-bit writable counter which
causes an interrupt when bit 31 is set. The PerfControl
register is a 32-bit register containing a five bit field which
selects one of twenty-two event types as well as a handful
of bits which control the overall counting function. Note
that only one event type can be counted at a time and that
counting can occur for user code, kernel code, or both. The
event types and control bits are listed in Table 10.
The performance counter interrupt will only occur when
interrupts are enabled in the Status register, IE=1, and
Interrupt Mask bit 13 (IM[13]) of the coprocessor 0
interrupt control register is not set.
Since the performance counter can be set up to count
Table 10 – Performance Counter Control
PerfControl
Field
Description
4..0
Event Type
00: Clock cycles
01: Total instructions issued
02: Floating-point instructions issued
03: Integer instructions issued
04: Load instructions issued
05: Store instructions issued
06: Dual issued pairs
07: Branch prefetches
08: External Cache Misses
09: Stall cycles
0A: Secondary cache misses
0B: Instruction cache misses
0C: Data cache misses
0D: Data TLB misses
0E: Instruction TLB misses
0F: Joint TLB instruction misses
10: Joint TLB data misses
11: Branches taken
4.0 con’t
12: Branches issued
13: Secondary cache writebacks
14: Primary cache writebacks
15: Dcache miss stall cycles (cycles
where both cache miss tokens
taken and a third address is
requested)
16: Cache misses
17: FP possible exception cycles
18: Slip Cycles due to multiplier busy
19: Coprocessor 0 slip cycles
1A: Slip cycles due to pending
non-blockingloads
1B: Write buffer full stall cycles
1C: Cache instruction stall cycles
1D: Multiplier stall cycles
1E: Stall cycles due to pending
non-blocking loads - stall start of
exception
7..5
Reserved (must be zero)
8
Count in Kernel Mode
0: Disable
1: Enable
9
Count in User Mode
0: Disable
1: Enable
10
Count Enable
0: Disable
1: Enable
31..11
Reserved (must be zero)
Table 10 – Performance Counter Control (cont)
PerfControl
Field
Description
Data0
Data1
Addr
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
SysClock
Data2
Data3
NData NData
Write
NData
NEOD
NData
Figure 8 – Processor Block Write
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACT-7000ASC-300F17I | 64-BIT, 300 MHz, RISC PROCESSOR, CQFP208 |
| ACT4445 | DATACOM, MIL-STD-1553 DATA BUS TRANSCEIVER, BCC64 |
| ACTS04KMSR-02 | ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14 |
| ACTS04DMSR-02 | ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14 |
| ACTS08DMSR | ACT SERIES, QUAD 2-INPUT AND GATE, CDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ACT7000SC | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17C | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17I | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17M | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17Q | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
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