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參數(shù)資料
| 型號： | ACT-7000ASC-225F24Q |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 225 MHz, RISC PROCESSOR, CQFP208 |
| 封裝： | 1.120 X 1.120 INCH, INVERTED, CERAMIC, QFP-208 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 231K |
| 代理商： | ACT-7000ASC-225F24Q |
SCD7000A Rev C
FEATURES
■
Full militarized PMC-Sierra RM7000A
microprocessor
■
Dual Issue symmetric superscalar
microprocessor with instruction prefetch
optimized for system level price/performance
●
225, 300, 350 MHz operating frequency
Consult Factory for latest speeds
●
MIPS IV Superset Instruction Set Architecture
■
High performance interface (RM52xx
compatible)
●
800 MB per second peak throughput
●
100 MHz max. freq., multiplexed address/data
●
Supports 1/2 clock multipliers (2, 2.5, 3, 3.5, 4,
4.5, 5, 6, 7, 8, 9)
●
IEEE 1149.1 JTAG (TAP) boundary scan
■
Integrated primary and secondary caches -
all are 4-way set associative with 32 byte line
size
●
16KB instruction
●
16KB data: non-blocking and write-back or
write-through
●
256KB on-chip secondary: unified,
non-blocking, block writeback
■
MIPS IV instruction set
●
Data PREFETCH instruction allows the
processor to overlap cache miss latency and
instruction execution
●
Floating point combined multiply-add
instruction increases performance in signal
processing and graphics applications
●
Conditional moves reduce branch frequency
●
Index address modes (register + register)
■
Embedded supply de-coupling capacitors
and additional PLL filter components
■
Integrated memory management unit
(ACT52xx compatible)
●
Fully associative joint TLB (shared by I and D
translations)
●
48 dual entries map 96 pages
●
4 entry DTLB and 4 entry ITLB
●
Variable page size (4KB to 16MB in 4x
increments)
■
Embedded application enhancements
●
Specialized DSP integer Multiply-Accumulate
instruction, (MAD/MADU) and
three-operand multiply instruction (MUL/U)
●
Per line cache locking in primaries and
secondary
●
Bypass secondary cache option
●
I&D Test/Break-point (Watch) registers for
emulation & debug
●
Performance counter for system and software
tuning & debug
●
Ten fully prioritized vectored interrupts -
6 external, 2 internal, 2 software
●
Fast Hit-Writeback-Invalidate and
Hit-Invalidate cache operations for efficient
cache management
■
High-performance floating point unit -
700M FLOPS maximum
●
Single cycle repeat rate for common
single-precision operations and some
double-precision operations
●
Single cycle repeat rate for single-precision
combined multiply-add operations
●
Two cycle repeat rate for double-precision
multiply and double-precision combined
multiply-add operations
■
Fully static CMOS design with dynamic
power down logic
●
Standby reduced power mode with WAIT
instruction
●
3 watts typical @ 1.8V Int., 3.3V I/O, 300MHz
■
208-lead CQFP, cavity-up package (F17)
■
208-lead CQFP, inverted footprint (F24),
with the same pin rotation as the commercial
PMC-Sierra RM5261A
ACT 7000ASC
Standard Products
October 9, 2009
64-Bit Superscaler Microprocessor
www.aeroflex.com/Avionics
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACT-7000ASC-300F17I | 64-BIT, 300 MHz, RISC PROCESSOR, CQFP208 |
| ACT4445 | DATACOM, MIL-STD-1553 DATA BUS TRANSCEIVER, BCC64 |
| ACTS04KMSR-02 | ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14 |
| ACTS04DMSR-02 | ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14 |
| ACTS08DMSR | ACT SERIES, QUAD 2-INPUT AND GATE, CDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACT7000SC | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17C | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17I | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17M | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17Q | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
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