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參數(shù)資料
| 型號： | ACS8946T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 4
www.semtech.com
ACS8946 JAM PLL
Table 2 Internally Connected (IC) Pin
Pin No.
Symbol
I/O
Type
Description
37
IC1
-
Internally Connected: Connect to ground.
Table 3 Functional Pins
Pin No.
Symbol
I/O
Type
Description
2OUT1N
O
CML or
LVPECL
One of four CML or LVPECL differential outputs, partnered with pin 3; programmable at
spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT1 and OUT2 only,
output frequency can be instantly configured using Rate Selection pins (pins 47 and 48
for OUT1), from a set of four pre-configured “Available Rates”. See“Configuration” on
page 13. Output is on when VDD01 is supplied with 3.3 V, or off when VDD01 is tied to
zero volts. If VDD01 is connected to 0 V remove external biasing resistors.
3OUT1P
O
CML or
LVPECL
CML or LVPECL differential output partnered with pin 2. See pin 2 description for more
detail.
5OUT2N
O
CML or
LVPECL
One of four CML or LVPECL differential outputs, partnered with pin 6; programmable at
spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT1 and OUT2 only,
output frequency can be instantly configured using Rate Selection pins (pins 45 and 46
for OUT2), from a set of four pre-configured “Available Rates”. See“Configuration” on
page 13. Output is on when VDD02 is supplied with 3.3 V, or off when VDD02 is tied to
zero volts. If VDD02 is connected to 0 V remove external biasing resistors.
6OUT2P
O
CML or
LVPECL
CML or LVPECL differential output partnered with pin 5. See pin 5 description for more
detail.
8OUT3N
O
CML or
LVPECL
One of four CML or LVPECL differential outputs, partnered with pin 9; programmable at
spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT3 and OUT4 only,
the output frequency selection is controlled at power-up or on reset from a set of four
pre-configured “Available Rates”. See“Configuration” on page 13. Output is on when
VDD03 is supplied with 3.3 V, or off when VDD03 is tied to zero volts. If VDD03 is
connected to 0 V remove external biasing resistors.
9OUT3P
O
CML or
LVPECL
CML or LVPECL differential output partnered with pin 8. See pin 8 description for more
detail.
11
OUT4N
O
CML or
LVPECL
One of four CML or LVPECL differential outputs, partnered with pin 12; programmable at
spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT3 and OUT4 only,
the output frequency selection is controlled at power-up or on reset from a set of four
pre-configured “Available Rates”. See“Configuration” on page 13. Output is on when
VDD04 is supplied with 3.3 V, or off when VDD04 is tied to zero volts. If VDD04 is
connected to 0 V remove external biasing resistors.
12
OUT4P
O
CML or
LVPECL
CML or LVPECL differential output partnered with pin 11. See pin 11 description for more
detail.
13
ALARM1_CO0
O
LVTTL/
LVCMOS
Activity alarm output for the CLK1P/CLK1N input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up, where it is
used as a configuration output pin, that may be connected to CFG_IN[0:7] input pins as
required. See “Configuration” on page 13.
14
ALARM2_CO1
O
LVTTL/
LVCMOS
Activity alarm output for the CLK2P/CLK2N input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up time, where it
is used as a configuration output pin, that may be connected to CFG_IN[0:7] input pins
as required. See “Configuration” on page 13.
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