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參數(shù)資料
| 型號： | ACS8946T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 1/40頁 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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Revision 3/November 2006 Semtech Corp.
Page 1
www.semtech.com
ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
Jitter Attenuating, Multiplying Phase Locked Loop,
with Protection Switch, for OC-12/STM-4 and GbE
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
The ACS8946 JAM PLL is a Jitter-Attenuating, Multiplying
differential Phase-Locked Loop, for generating low jitter
output clocks compliant up to SONET OC-12 and STM-4
622.08 MHz specifications. Its primary function is to
clean up clock jitter for high performance optical line
cards with OC-12 framers and serializers. It also provides
reference switching functionality for line card protection,
and frequency translation.
Typical output jitter generation is within OC-12/STM-4
specifications, at 2.8 ps rms, making it an ideal dejittering
solution for use with Semtech clock and line card parts:
ACS8510, ACS8520, ACS8522 and ACS8530. The
ACS8946 can also be used as a basic line card protection
device in some applications.
The ACS8946 JAM PLL has two differential, frequency
programmable, LVPECL reference inputs and one
differential sync input. It has four outputs, programmable
as LVPECL or CML, and frequency programmable to any
common SONET/SDH rate i.e. 19.44 MHz, 38.88 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz and 622.08 MHz.
Jitter cleaning of Gigabit Ethernet (GbE) 125 MHz and
156.25 MHz is also possible, with output frequency
multiplication up to 625.00 MHz available.
The device's operating bandwidth (and consequently the
jitter attenuation point relating to this bandwidth) is fully
configurable, and is set by external passive components.
Note...For items marked [1],[2], etc. references are given in full
in the Reference Section on page 38.
Meets rms jitter requirements of:
Telcordia GR-253[8] for OC-3 and OC-12
ITU-T G.813[4]/G.812[3] for STM-1 and STM-4 rates
rates
PLL bandwidth and jitter peaking fully adjustable—
supports PLL loop bandwidths from 2 kHz for superior
input jitter filtering
Typical jitter generation down to:
0.3 ps rms for 250 kHz to 5 MHz band for G.813,
or EN300 462, at STM-4 (OC-12) rates
2.8 ps rms for 12 kHz to 20 MHz band (against
4.02 ps rms for GR-253-CORE at OC-48 rate)
ITU, ETSI and Telcordia frequency band results shows
exceptional performance in a “Real World”
environment (low PLL bandwidth of 2 KHz and a
typical input from an ACS8525 partner IC):
0.4 ps rms for 250 kHz to 5 MHz band for G.813,
or EN300 462, at STM-4 (OC-12) rates
2.8 ps rms for 12 kHz to 20 MHz band
Tracking range ±400 ppm about a wide range of input
frequencies
Manual or automatic control of reference selection
External feedback option
LOS alarms for each input, and for selected reference
3.3 V operation, - 40 to +85°C temperature range
Small outline leadless 7 mm x 7 mm QFN48 package
Lead (Pb)-free version available (ACS8946T),
Figure 1 Simplified Block Diagram of the ACS8946 JAM PLL
Block Diagram
Introduction
Features
Loop
Filter
Re-timing
PFD
Charge
Pump
2.5 GHz
VCO
Divider
Frequency
Dividers
Clock
Drivers
Input
Selector
Control and Monitor
4 x LVPECL or CML
Output Clocks,
Independently
Programmable
from:
625.00 MHz
622.08 MHz
311.04 MHz
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
125 MHz
156.25 MHz
Others Ethernet rates
available using divider
SYNC_OUT
OUT[4:1]
SYNC
CLK1
CLK2
Clock Input Configuration for:
- Manual selection
- Auto Ref selection
- External feedback mode
(SEL_CLK2, AUTO_SEL)
LOS Alarms for:
- CLK1 (ALARM1_CO0)
- CLK2 (ALARM2_CO1)
- Currently selected reference (ALARMC_CO3)
Lock Alarm (LOCKB)
Input References
Programmable:
19.44 MHz to
156.25 MHz
RESETB
CFG_IN[7:0]
CFG_OUT2
Device Configuration Select:
Frequency Select
(RATE[2:1]A, RATE[2:1]B)
VC
F8946D_004Blockdiag_06
2 x LVPECL
Differential
1 x LVPECL
Differential Sync Input
1 x CMOS
Single-ended
Sync Output
Note: LOS alarm outputs are also
used for device config. select
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