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參數(shù)資料
| 型號(hào)： | ACH16843DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | JT 6C 6#20 PIN PLUG |
| 中文描述： | ALVC/VCX/A SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 84K |
| 代理商： | ACH16843DGG |
Philips Semiconductors
Product specification
74ALVCH16843
18-bit bus interface D-type latch (3-State)
1998 Aug 04
8
AC WAVEFORMS FOR V
CC
= 2.3V TO 2.7V AND
V
CC
< 2.3V RANGE
V
M
= 0.5 V
V
X
= V
OL
+ 0.15V
V
Y
= V
OH
–0.15V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
VI
= V
CC
AC WAVEFORMS FOR V
CC
= 3.0V TO 3.6V AND
V
CC
= 2.7V RANGE
V
M
= 1.5 V
V
X
= V
OL
+ 0.3V
V
Y
= V
–0.3V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
VI
= 2.7V
t
PHL
t
PLH
V
OL
CLR, D
n
V
I
PRE GND
V
OH
Q
n
OUTPUT
V
M
V
M
SH00147
Waveform 1. Data input (Dn) to output (Qn), clear input (CLR)
to output (Qn) and preset input (PRE) to output (Qn)
propagation delay
LE INPUT
Qn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
V
M
V
M
V
M
SH00150
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Qn) propagation delay
ééé
ééé
ééééééééé
ééééééééé
ééééééééé
Dn
INPUT
LE
INPUT
t
SU
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
t
SU
V
GND
V
I
GND
V
M
V
M
SH00149
Waveform 3. Data set-up and hold times for the Dn input to the
LE input
CLR, PRE
t
W(L)
t
REM
V
I
GND
LE
V
M
V
M
SH00148
V
I
GND
Waveform 4. Clear (CLR) and preset (PRE) pulse width, the
clear (CLR) and preset (PRE) to latch (LE) removal time
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SH00137
Waveform 5. 3-State enable and disable times
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