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參數(shù)資料
| 型號(hào)： | ACH16843DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | JT 6C 6#20 PIN PLUG |
| 中文描述： | ALVC/VCX/A SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 84K |
| 代理商： | ACH16843DGG |
Philips Semiconductors
Product specification
74ALVCH16843
18-bit bus interface D-type latch (3-State)
2
1998 Aug 04
853–2108 019833
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
±
24 mA at 3.0 V
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
All data inputs have bus hold
Output drive capability 50
transmission lines @ 85
°
C
DESCRIPTION
The 74ALVCH16843 has two 9–bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE), clear (nCLR),
preset (nPRE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs.
When nOE is HIGH, the outputs are in the high impedance OFF
state. Operation of the nOE input does not affect the state of the
flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1OE
1Q
0
1Q
1
1Q
2
1Q
3
1Q
4
1Q
5
GND
V
CC
GND
1Q
6
1Q
7
1Q
8
2Q
0
2Q
1
2Q
2
GND
2Q
3
2Q
4
2Q
5
V
CC
2Q
6
2Q
7
GND
2Q
8
2CLR
1D
0
GND
1D
1
1D
2
V
CC
1D
3
1D
4
1D
5
GND
1D
6
1D
7
1D
8
2D
0
2D
1
2D
2
GND
2D
3
2D
4
2D
5
V
CC
2D
6
2D
7
GND
2D
8
2LE
1PRE
1CLR
2OE
1LE
2PRE
SH00143
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5ns
SYMBOL
Propagation delay
nDn to nQn
Propagation delay
nLE to nQn
C
I
Input capacitance
PARAMETER
CONDITIONS
TYPICAL
2.2
2.1
2.3
2.0
5.0
UNIT
t
PHL
/t
PLH
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
ns
ns
pF
C
PD
Power dissipation capacitance per buffer
Power dissi ation ca acitance er buffer
V
I
= GND to V
CC1
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
17
3
pF
19
9
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
–40
°
C to +85
°
C
OUTSIDE NORTH
AMERICA
74ALVCH16843 DGG
NORTH AMERICA
DRAWING
NUMBER
SOT364-1
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
ACH16843 DGG
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