參數(shù)資料
型號(hào): ACE1501EMTX
廠商: Fairchild Semiconductor Corporation
英文描述: ACE1501 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
中文描述: ACE1501產(chǎn)品系列運(yùn)算控制器引擎(ACEx⑩)的低功耗應(yīng)用
文件頁(yè)數(shù): 15/33頁(yè)
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代理商: ACE1501EMTX
A
)
15
www.fairchildsemi.com
ACE1501 Product Family Rev. 1.
1
The following steps show how to properly con
fi
gure Timer 1 to
operate in the PWM mode. For this example, the T1 output sig-
nal is toggled with every timer under
fl
ow and the
high
and
low
times for the T1 output can be set to different values. The
T1 output signal can start out either high or low depending on
the con
fi
guration of G2; the instructions below are for starting
with the T1 output high. Follow the instructions in parentheses
to start the T1 output low.
1. Con
fi
gure T1 as an output by setting bit 2 of PORTGC.
- SBIT 2, PORTGC
; Con
fi
gure G2 as an output
2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of
PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Load the initial PWM high (low) time into the timer register.
- LD
TMR1LO, #6FH
(1MHz clock)
- LD
TMR1HI, #05H
; High (Low) for 1.391ms
4. Load the PWM low (high) time into the T1RA register.
- LD
T1RALO, #2FH
(1MHz clock)
- LD
T1RAHI, #01H
; Low (High) for .303ms
5. Write the appropriate control value to the T1CNTRL register
to select PWM mode with T1 toggle, to clear the enable bit
and pending
fl
ag, and to start the timer. (See Table 11 and
Table 12.)
- LD
T1CNTRL, #0B0H
; Setting the T1C0 bit starts the
timer
6. After every under
fl
ow, load T1RA with alternate values. If the
user wishes to generate an interrupt on a T1 output transi-
tion, reset the pending
fl
ags and then enable the interrupt
using T1EN. The G bit must also be set. The interrupt
service routine must reset the pending
fl
ag and perform
whatever processing is desired.
- RBIT T1PND, T1CNTRL
; T1PND equals 3
- LD
T1RALO, #6FH
; High (Low) for 1.391ms
(1MHz clock)
- LD
T1RAHI, #05H
Figure 15. Pulse Width Modulation Mode
4.3 Mode 2: External Event Counter Mode
The External Event Counter mode operates similarly to the
PWM mode; however, the timer is not clocked by the instruction
clock but by transitions of the T1 input signal. The edge is
selectable through the T1C1 bit of the T1CNTRL register. A
block diagram of the timer
s External Event Counter mode of
operation is shown in Figure 16.
The T1 input should be connected to an external device that
generates a positive/negative-going pulse for each event. By
clocking the timer through T1, the number of positive/negative
transitions can be counted therefore allowing software to cap-
ture the number of events that occur. The input signal on T1
must have a pulse width equal to or greater than one instruction
clock cycle.
The counter can be con
fi
gured to sense either positive-going or
negative-going transitions on the T1 pin. The maximum fre-
quency at which transitions can be sensed is one-half the fre-
quency of the instruction clock.
As with the PWM mode, when the counter under
fl
ows the
counter is reloaded from the T1RA register and the count down
proceeds from the loaded value. At every under
fl
ow, a pending
fl
ag (T1PND) located in the T1CNTRL register is set. Software
must then clear the T1PND
fl
ag and can then load the T1RA
register with an alternate value.
The counter has one interrupt (TMRI1) that is maskable through
the T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable)
bit of the SR is set. If interrupts are enabled, the counter will
generate an interrupt each time the T1PND
fl
ag is set (when-
ever timer under
fl
ows provided that the pending
fl
ag was
cleared.) The interrupt service routine is responsible for proper
handling of the T1PND
fl
ag and the T1EN bit.
The following steps show how to properly con
fi
gure Timer 1 to
operate in the External Event Counter mode. For this example,
the counter is clocked every falling edge of the T1 input signal.
Follow the instructions in parentheses to clock the counter every
rising edge.
1. Con
fi
gure T1 as an input by clearing bit 2 of PORTGC.
- RBIT
2, PORTGC
; Con
fi
gure G2 as an input
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
- SBIT
2, PORTGD
; Set G2 high
3. Enable the global interrupt enable bit.
- SBIT
4, STATUS
4. Load the initial count into the TMR1 and T1RA registers.
When the number of external events is detected, the counter
will reach zero; however, it will not under
fl
ow until the next
event is detected. To count N pulses, load the value N-1 into
the registers. If it is only necessary to count the number of
occurrences and no action needs to be taken at a particular
count, load the value 0xFFFF into the registers.
- LD
TMR1LO, #0FFH
- LD
TMR1HI, #0FFH
- LD
T1RALO, #0FFH
- LD
T1RAHI, #0FFH
Data
Bus
16-bit Auto-Reload
Register (T1RA)
Data
Latch
T1
Underflow
Interrupt
Instruction
Clock
16-bit Auto-Reload
Register (T1RB)
1
0
S
T1RBEN
Reload select logic
16-bit Timer (TMR1)
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ACE1501EMX ACE1501 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
ACE1501EN ACE1501 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
ACE1501VM ACE1501 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
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參數(shù)描述
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ACE1501EN 功能描述:8位微控制器 -MCU arithmetic Controllr Engine RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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ACE1501V 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:ACE1501 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
ACE1501VM 功能描述:8位微控制器 -MCU arithmetic Controllr Engine RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT