參數(shù)資料
型號(hào): AAT1236IRN-T1
廠商: Advanced Analog Technology,lnc.
元件分類: LED驅(qū)動(dòng)器
英文描述: High Efficiency White LED Drivers for Backlight and Keypad
中文描述: 高效率白光LED的背光和鍵盤驅(qū)動(dòng)程序
文件頁數(shù): 13/24頁
文件大小: 1009K
代理商: AAT1236IRN-T1
AAT1236
High Efficiency White LED Drivers
for Backlight and Keypad
1236.2007.02.1.1
13
Application Information
I
2
C Serial Interface
The AAT1236 is fully compliant with the industry-
standard I
2
C interface. The I
2
C two-wire communica-
tions bus consists of SDA and SCL lines. SDA pro-
vides data, while SCL provides clock synchroniza-
tion. SDA data transfers device address followed by
a register address and data bits sequence. When
using the I
2
C interface, EN/SET is pulled high to
enable the device or low to disable the device. The
I
2
C serial interface requires a master to initiate all the
communications with target devices. The AAT1236
is a target device and only supports the write proto-
col. The AAT1236 is manufactured with a target
device address of 0x36 (Hex). See Figure 1 for the
I
2
C interface diagram.
I
2
C START and STOP Conditions
START and STOP conditions are always generat-
ed by the master. Prior to initiating a START, both
the SDA and SCL pins are in idle mode (idle mode
is when there is no activity on the bus and both
SDA and SCL are pulled high by the external pull-
up resistors). A START condition occurs when the
master pulls the SDA line low and, after a short
period, pulls the SCL line low. A START condition
acts as a signal to all ICs that transmission activity
is about to occur on the BUS. A STOP condition,
as shown in Figure 2, is when the master releases
the bus and SCL changes from low to high followed
by SDA low-to-high transition.
I
2
C Address Bit Map
Figure 3 illustrates the address bit transfer. The 7-
bit address is transferred with the Most Significant
Bit (MSB) first and is valid when SCL is high. This
is followed by the R/W bit in the Least Significant
Bit (LSB) location. The R/W bit determines the
direction of the transfer ('1' for read, '0' for write).
The AAT1236 is a write-only device and this bit
must be set low. The Acknowledge bit (ACK) is set
to low by the AAT1236 to acknowledge receipt of
the address.
I
2
C Register Address / Data Bit Map
Figure 4 illustrates the Register Address or the data
bit transfer. The 8-bit data is always transferred
with the most significant bit first and is valid when
SCL is high. The Acknowledge bit (ACK) is set low
by the AAT1236 to acknowledge receipt of the reg-
ister address or the data.
I
2
C Acknowledge Bit (ACK)
The Acknowledge bit is the ninth bit of each trans-
fer on the SDA line. It is used to send back a con-
firmation to the master that the data has been
received properly by the target device. For each
ACK to take place, the master must first release the
SDA line, then the target device will pull the SDA
line low, as shown in Figures 1, 3 and 4.
Figure 1: I
2
C Serial Interface Diagram.
AAT1236 Device Addr = 36h
w
ACK
Address = 00h
ACK
Data = 06h
ACK
stop
start
SDA
SCL
start
Device Address
w
ACK
Register Address
ACK
DATA
ACK
stop
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