參數(shù)資料
型號(hào): A8905CLB
廠商: Allegro MicroSystems, Inc.
英文描述: 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
中文描述: 3相無(wú)刷直流電動(dòng)機(jī)控制器/驅(qū)動(dòng)器,反電動(dòng)勢(shì)遙感
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 163K
代理商: A8905CLB
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
TERMINAL FUNCTIONS
Term.
Terminal Name
Function
1
LOAD SUPPLY
V
BB
; the 5 V or 12 V motor supply.
2
C
D2
One of two capacitors used to generate the ideal commutation points from the back-EMF
zero-crossing points.
3
C
WD
Timing capacitor used by the watchdog circuit to disable the back-EMF comparators
during commutation transients, and to detect incorrect motor position.
4
C
ST
Startup oscillator timing capacitor.
5
OUT
A
Power amplifier output A to motor.
6-7
GROUND
Power and logic ground and thermal heat sink.
8
OUT
B
Power amplifier output B to motor.
9
OUT
C
Power amplifier output C to motor.
10
CENTERTAP
Motor centertap connection for back-EMF detection circuitry.
11
BRAKE
Active low turns ON all three sink drivers shorting the motor windings to ground. External
capacitor and resistor at B
RAKE
provide brake delay. The brake function can also be
controlled via the serial port.
12
C
RES
External reservoir capacitor used to hold charge to drive the source drivers’ gates. Also
provides power for brake circuit.
13
FILTER
Analog voltage input to control motor current. Also, compensation node for internal speed
control loop.
14
INDEX
External tachometer input.
15
LOGIC SUPPLY
V
DD
; the 5 V logic supply.
16
OSCILLATOR
Clock input for the speed reference counter. Typical max. frequency is 10 MHz.
17
DATA OUT
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real time,
controlled by 2-bit multiplexer in serial port.
18-19
GROUND
Power and logic ground and thermal heat sink.
20
RESET
When pulled low forces the chip into sleep mode; clears all serial port bits.
21
CHIP SELECT
Strobe input (active low) for data word.
22
CLOCK
Clock input for serial port.
23
DATA IN
Sequential data input for the serial port.
24
C
D1
One of two capacitors used to generate the ideal commutation points from the back-EMF
zero-crossing points.
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