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參數(shù)資料
| 型號： | A8351601SERIES |
| 英文描述： | Bar Code Reader |
| 中文描述： | 條碼閱讀器 |
| 文件頁數(shù)： | 9/43頁 |
| 文件大?。?/td> | 413K |
| 代理商： | A8351601SERIES |
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A8351601 Series
PRELIMINARY (October, 2001, Version 0.5)
8
AMIC Technology, Inc.
PCON:
Power Control Register. Not Bit Addressable.
7
6
-
5
-
4
-
3
2
1
PD
0
SMOD
Register Description:
SMOD
GF1
GF0
IDL
Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD=1, the baud rate is doubled when
the serial port is used in modes 1, 2, or 3.
Not implemented, reserve for future use.
(1)
Not implemented, reserve for future use.
(1)
Not implemented, reserve for future use.
(1)
General purpose flag bit.
General purpose flag bit.
Power-down bit. Setting this bit activates power-down operation in the A8351601.
Idle mode bit. Setting this bit activates idle mode operation in the A8351601. If 1s are written to PD and IDL
at the same time, PD takes precedence.
-
-
-
GF1
GF0
PD
IDL
Note:
1. User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features.
IE
Interrupt Enable Register. Bit Addressable.
7
EA
6
-
5
4
ES
3
2
1
0
ET2
ET1
EX1
ET0
EX0
Register Description:
EA
IE.7
Disable all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
Not implemented, reserve for future use.
(5)
Enables or disables timer 2 overflow interrupt.
Enable or disable the serial port interrupt.
Enable or disable the timer 1 overflow interrupt.
EX1 IE.2 Enable or disable external interrupt 1.
Enable or disable the timer 0 overflow interrupt.
Enable or disable external interrupt 0.
-
ET2
ES
ET1
EX1
ET0
EX0
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Note:
To use any of the interrupts in the 80C51 Family, the following three steps must be taken:
1. Set the
EA
(enable all) bit in the IE register to 1.
2. Set the corresponding individual interrupt enable bit in the IE register to 1.
3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt (see below).
Interrupt Source Vector Address
IE0
TF0
IE1
TF1
RI & TI
TF2 and EXF2
0003H
000BH
0013H
001BH
0023H
002BH
4. In addition, for external interrupts, pins
INT0
and INT1 (P3.2 and P3.3) must be set to 1, and depending on whether the
interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need to be set to 0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5. User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features.
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| A83516-12 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:8 Bit Microcontroller |
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| A83516-40 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:8 Bit Microcontroller |
| A83516L-12 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:8 Bit Microcontroller |
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