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參數(shù)資料
| 型號： | A63G7332E-45 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| 中文描述： | 128K的× 32位同步高的Burst計數(shù)器和流水線數(shù)據(jù)輸出高速SRAM |
| 文件頁數(shù)： | 14/17頁 |
| 文件大小： | 382K |
| 代理商： | A63G7332E-45 |
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1)
13
AMIC Technology, Inc.
Timing Waveforms (continued)
CLK
ADSP
ADSC
ADDRESS
A1
A3
CE
(NOTE *2)
ADV
OE
D(A3)
D(A5)
D(A6)
High-Z
DIN
t
CEH
t
CES
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
A2
A4
A5
A6
GW,BWE,
BW1-BW4
(NOTE *3)
High-Z
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
DOUT
Back-to-Back READs
Single WRITE
Pass-through
READ
(NOTE *4)
BURST READ
Back-to-Back
WRITEs
(NOTE *1)
t
KQ
t
OELZ
t
DH
t
DS
t
OEHZ
t
KQ
t
KQLZ
t
WS
t
WH
t
AS
t
AH
Read/Write Timing
Notes:
*1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the internal burst address immediately
following A4.
*2. Timing for
CE2
and CE2 is identical to that for
CE
. As shown in this diagram, when
CE
is LOW,
CE2
is
LOW and CE2 is HIGH. When
CE
is HIGH,
CE2
is HIGH and CE2 is LOW.
*3. Byte Write enables are decided by means of a Write truth table.
*4. Pass-through occurs when data is first written, then Read in sequence.
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