參數資料
型號: A54SX72A-TQ208B
廠商: Electronic Theatre Controls, Inc.
英文描述: Hex Buffers / Drivers with Open-Collector High-Vltage Outputs 14-PDIP 0 to 70
中文描述: 的SX - A系列FPGA的
文件頁數: 63/108頁
文件大?。?/td> 720K
代理商: A54SX72A-TQ208B
SX-A Family FPGAs
v5.1
2-43
t
INYL
Input Data Pad to Y Low 5 V PCI
0.8
0.9
1.0
1.2
1.6
ns
t
INYH
Input Data Pad to Y High 5 V TTL
0.7
0.8
0.9
1.0
1.4
ns
t
INYL
Input Module Predicted Routing Delays2
Input Data Pad to Y Low 5 V TTL
0.9
1.1
1.2
1.4
1.9
ns
t
IRD1
FO = 1 Routing Delay
0.3
0.3
0.4
0.5
0.7
ns
t
IRD2
FO = 2 Routing Delay
0.4
0.5
0.6
0.7
1
ns
t
IRD3
FO = 3 Routing Delay
0.5
0.7
0.8
0.9
1.3
ns
t
IRD4
FO = 4 Routing Delay
0.7
0.9
1
1.1
1.5
ns
t
IRD8
FO = 8 Routing Delay
1.2
1.5
1.7
2.1
2.9
ns
t
IRD12
FO = 12 Routing Delay
1.7
2.2
2.5
3
4.2
ns
Table 2-35
A54SX72A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, V
CCA
= 2.25 V
,
V
CCI
= 3.0 V, T
J
= 70
°
C)
Parameter
Description
–3 Speed
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
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