
SX-A Family FPGAs
v5.1
1-7
Other Architectural Features
Technology
The Actel SX-A family is implemented on a high-voltage,
twin-well CMOS process using 0.22
μ
/ 0.25
μ
design
rules. The metal-to-metal antifuse is comprised of a
combination of amorphous silicon and dielectric material
with barrier metals and has a programmed ('on' state)
resistance of 25
with capacitance of 1.0 fF for low
signal impedance.
Performance
The unique architectural features of the SX-A family
enable the devices to operate with internal clock
frequencies of 350 MHz, causing very fast execution of
even complex logic functions. The SX-A family is an
optimal platform upon which to integrate the
functionality previously contained in multiple complex
programmable logic devices (CPLDs). In addition, designs
that previously would have required a gate array to meet
performance goals can be integrated into an SX-A device
with dramatic improvements in cost and time-to-market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
User Security
Reverse engineering is virtually impossible in SX-A
devices because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses. In
addition, since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept at device
power-up.
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
where they cannot be accessed or bypassed without
destroying access to the rest of the device, making both
invasive and more-subtle noninvasive attacks ineffective
against Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure
(
Figure 1-11
).
Implementation of