參數(shù)資料
型號： A42MX16-2PL100
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 24/123頁
文件大?。?/td> 854K
代理商： A42MX16-2PL100
40MX and 42MX FPGA Families
1-18
v6.0
Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only)
Mixed 5.0V/3.3V Electrical Specifications
Table 14
Absolute Maximum Ratings*
Symbol
Parameter
Limits
Units
V
CCI
V
CCA
V
I
V
O
t
STG
Note:
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
DC Supply Voltage for I/Os
–0.5 to +7.0
V
DC Supply Voltage for Array
–0.5 to +7.0
V
Input Voltage
–0.5 to V
CCI
+0.5
–0.5 to V
CCI
+0.5
–65 to +150
V
Output Voltage
V
Storage Temperature
°C
Table 15
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
Temperature Range*
0 to +70
-40 to +85
–55 to +125
°C
V
CCA
V
CCI
Note:
*Ambient temperature (T
A
) is used for commercial and industrial grades; case temperature (T
C
) is used for military grades.
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
3.14 to 3.47
3.0 to 3.6
3.0 to 3.6
V
Table 16
Mixed 5.0V/3.3V Electrical Specifications
Symbol
Parameter
Commercial
Commercial '-F
'Industrial
Military
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
V
OH1
I
OH
= –10mA
I
OH
= –4mA
I
OL
= 10mA
I
OL
= 6mA
2.4
2.4
V
3.7
3.7
V
V
OL1
0.5
0.5
V
0.4
0.4
V
V
IL
V
IH
I
L
I
H
Input Transition Time, T
R
and T
F
C
IO
I/O Capacitance
Standby Current, I
CC2
–0.3
0.8
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
2.0
V
CCI
+0.3
–10
2.0
V
CCI
+0.3
–10
2.0
V
CCI
+0.3
–10
2.0
V
CCI
+0.3
–10
V
V
IN
= 0.5V
V
IN
= 2.7V
μA
–10
–10
–10
–10
μA
500
500
500
500
ns
10
10
10
10
pF
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24, A42MX36
20
25
25
25
mA
Low-Power Mode Standby Current
0.5
I
CC
- 5.0
I
CC
- 5.0
I
CC
- 5.0
mA
I
IO
I/O source sink current
Notes:
1. Only one output tested at a time. V
CCI
= min.
2. All outputs unloaded. All inputs = V
CCI
or GND.
IBIS model
相關(guān)PDF資料
PDF描述
A42MX16-2PL100A Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85
A42MX16-2PL100B Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85
A42MX16-2PL100ES 40MX and 42MX FPGA Families
A42MX16-2PL100I Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85
A42MX16-2PL100M Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-2PL100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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