參數(shù)資料
型號： A42MX16-2PL100
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 21/123頁
文件大?。?/td> 854K
代理商： A42MX16-2PL100
40MX and 42MX FPGA Families
v6.0
1-15
5V TTL Electrical Specifications
Table 9
5V TTL Electrical Specifications
Symbol
Parameter
Commercial
Commercial -F
Industrial
Military
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
V
OH1
I
OH
= -10mA
2.4
2.4
V
I
OH
= -4mA
3.7
3.7
V
V
OL1
I
OL
= 10mA
0.5
0.5
V
I
OL
= 6mA
0.4
0.4
V
V
IL
-0.3
0.8
-0.3
0.8
-0.3
0.8
-0.3
0.8
V
V
IH
(40MX)
2.0
V
CC
+0.3
2.0
V
CC
+0.3
2.0
V
CC
+0.3
2.0
V
CC
+0.3
V
V
IH
(42MX)
2.0
V
CCI
+0.3
2.0
V
CCI
+0.3
2.0
V
CCI
+0.3
2.0
V
CCI
+0.3
V
I
IL
V
IN
= 0.5V
-10
-10
-10
-10
μA
I
IH
V
IN
= 2.7V
-10
-10
-10
-10
μA
Input
Time, T
R
and T
F
Transition
500
500
500
500
ns
C
IO
I/O Capacitance
10
10
10
10
pF
Standby
I
CC2
Current,
A40MX02,
A40MX04
3
25
10
25
mA
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
20
25
25
25
mA
Low-Power
Standby Current
Mode
42MX devices
only
0.5
I
CC
- 5.0
I
CC
- 5.0
I
CC
- 5.0
mA
I
IO
,
I/O source sink
current
IBIS model
相關(guān)PDF資料
PDF描述
A42MX16-2PL100A Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85
A42MX16-2PL100B Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85
A42MX16-2PL100ES 40MX and 42MX FPGA Families
A42MX16-2PL100I Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85
A42MX16-2PL100M Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-2PL100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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