參數(shù)資料
型號： A42MX16-2CQ100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 8/120頁
文件大小： 854K
代理商： A42MX16-2CQ100
105
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit 5 - T3CRMB: Timer3 Compare Reset Mask Bit B
The T3CRMB bit must be written to logic one to enable the counter reset if a match of the coun-
ter with the compare register B (T3CORB) occurs. If the T3CRMB bit is written to logic zero, the
counter compare reset is disabled.
Bit 4 - T3SAMB: Timer3 Single Action Mask Bit B
The T3SAMB bit must be written to logic one to enable the single-compare mode, and if the
T3SAMB bit is written to logic zero, the single-compare mode is disabled. After this bit is set, a
compare match of the counter with register B (T3CORB) is generated only one time.
Bit 3 - T3CTMB: Timer3 Compare Toggle Mask Bit B
The T3CTMB bit must be written to logic one to enable the compare toggle, and if the T3CTMB
bit is written to logic zero, the compare toggle is disabled. A match of the counter with the com-
pare register B (T3CORB) toggles the output flip-flop in the modulator of the Timer3.
Bit 2 - T3CRMA: Timer3 Compare Reset Mask Bit A
The T3CRMA bit must be written to logic one to enable the counter reset if a match of the coun-
ter with the compare register A (T3CORA) occurs. If the T3CRMA bit is written to logic zero, the
counter compare reset is disabled.
Bit 1 - T3SAMA: Timer3 Single Action Mask Bit A
The T3SAMA bit must be written to logic one to enable the single-compare mode, and if the
T3SAMA bit is written to logic zero, the single-compare mode is disabled. After this bit is set, a
compare match of the counter with register A (T3CORA) is generated only one time.
Bit 0 - T3CTMA: Timer3 Compare Toggle Mask bit A
The T3CTMA bit must be written to logic one to enable the compare toggle, and if the T3CTMA
bit is written to logic zero, the compare toggle is disabled. A match of the counter with the com-
pare register A (T3CORA) toggles the output flip-flop in the modulator of the Timer3.
3.13.7.5
Timer3 Mode Register A – T3MRA
Bits 7 to 6 – T3ICS1..0: Timer 3 Input Capture Select Bits 1 to 0
The T3ICS1 and T3ICS0 bits select the input capture signal of theTimer3, shown in Table 3-42.
Bit
7
6543210
T3ICS1
T3ICS0
T3CNC
T3CE1
T3CE0
T3CS2
T3CS1
T3CS0
T3MRA
Read/Write
R/W
Initial Value
0
0000000
Table 3-42.
Input Capture Signal Select Bit Description
T3ICS1
T3ICS0
Description
00
T3ICP
01
LFDO
10
CLKT1
11
CLKT2
相關(guān)PDF資料
PDF描述
A42MX24-2CQ100 40MX and 42MX FPGA Families
A42MX36-2CQ100 Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:2m; No. of Contacts:12; No. of Positions:12 RoHS Compliant: Yes
A42MX02-2CQ100A Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:Stripped End Leads; Cable Length:5m; No. of Contacts:12; No. of Positions:12 RoHS Compliant: Yes
A42MX04-2CQ100A Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:5m; No. of Contacts:12; No. of Positions:12 RoHS Compliant: Yes
A42MX09-2CQ100A 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-2CQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2CQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2CQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2CQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2CQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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