參數(shù)資料
型號(hào): A42MX16-2CQ100
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 14/120頁
文件大小: 854K
代理商: A42MX16-2CQ100
110
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.7.11
Timer3 Mode Register B – T3MRB
Bits 7..5 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 4 - T3TOP: Timer3 Toggle Output Preset Bit
The T3TOP bit must be written to logic one to set the toggle flip-flop, and if the T3TOP bit is writ-
ten to logic zero, the toggle flip-flop is reset. This bit allows the programmer to preset the toggle
output flip-flop in the modulator of the Timer3.
Note:
If T3E = “1”, no output preset is possible
Bit 3 - Res: Reserved Bit
This bit is reserved bit at the ATA6289 and will always read as zero.
Bits 2..0 - T3M2..0: Timer3 Mode Bits 2 - 0
The T3M2,T3M1 and T3M0 bits select the output mode of theTimer3 as shown in Table 3-45.
Bit
76
54
32
10
-
T3TOP
-
T3M2
T3M1
T3M0
T3MRB
Read/Write
R
R/W
R
R/W
Initial Value
00
Table 3-45.
Timer3 Mode Bit Description
Mode
T3M2
T3M1
T3M0
Timer3 Mode
T3O(1)
1
0
Timer/Counter Mode
PB1
2
0
1
Toggle Mode
M30
3
0
1
0
Burst modulation with Timer2 (M2)
M31
4
0
1
Capture Mode
PB1
5
1
0
Capture Mode
M30
6
1
0
1
Sensor Measurement Mode together with Timer2
PB1
7
110
Reserved
PB1
8
111
Reserved
PB1
Note:
General Port I/O: PB1
Alternate port function:
Output signal of the T3 (toggle flip-flop): M30 or M31 = M30 and M2
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