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參數(shù)資料
| 型號： | A42MX16-2BG100ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 118/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2BG100ES |
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97
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.6.5
Mode 5: PWM Mode with Modulator Output T2O2 at the PD6 Pin
The Timer/Counter2 can be supplied with internal/external clocks. Mode 5 uses only one modu-
lator I/O pin (M2 --> T2O2) to work as pulse width modulator for different frequencies. The port
pins (PD5, PD7) can be used as general digital I/O. The timer has four different programmable
fixed TOP values, which can be selected with the T2TP[1..0] bits in the T2MRA and the modula-
tor output of Timer2 is toggled when the timer is enabled with T2E. Figure 3-41 shows an
example of a PWM signal generation.
Figure 3-41. PWM Mode and Modulator Output at the T2O2 Pin, Timing Diagram
3.13.6.6
Mode 6: Modulator Mode with SSI and Modulator Output T2O1 at the PD5 Pin
The Timer2/Counter2 can be supplied with internal/external clocks. Mode 6 uses only one mod-
ulator I/O pin (SO --> T2O1). The port pins (PD6, PD7) can be used as general digital I/O. The
timer output clock (CLK
T2) can be used to supply the SSI with shift clock. Together with the con-
tinuous serial data stream generated by Synchronous Serial Interface (SSI) the modulator mode
6 of the timer allows the generation of Biphase code, Manchester code or PWM code. Figure
3-42 shows an example of Manchester code generation.
Figure 3-42. Modulator Mode and Modulator Output at the T2O1 Pin, Timing Diagram
Manchester Code:
Rising edge in the middle of the bit
→High, falling edge in the middle of
the bit
→Low.
In the same moment the 8-bit Shift register (SR) is loaded with the T2MDR (TXD) data the first
bit (MSB) will appear at T201 output pin.
TOP value update by
overflow interrupt
T2CNT
0xFFFF
TOP
values
T2E
T2O2
0x00FF
0x01FF
0x03FF
fixed compare value
0x9A
0xA6
0x65
T2MDR
(TXD)
Manchester coded
bit stream
Load 8-bit Shift
Register (SR)
T2SSIE
Shifted value of 8-bit
Shift Register (SR)
T201
SCLK
CLKT2
Bit 3 = ’1’
Bit 2 = ’1’
Bit 4 = ’0’
Bit 9 = ’1’
Bit 8 = ’0’
Bit 10 = ’0’
Bit 6 = ’1’
Bit 7 = ’0’
Bit 5 = ’0’
Bit 1 = ’0’
Bit 0 = ’1’
0x50
0x28
0x94
0xCA
0x65
0x34
0x40
0xA0
0x68
0xD0
0x9A
0x00
0x98
0x80
0xC0
0x30
0x60
0xA0
0x4C
0xA6
0x40
0x80
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2BG100ES | Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:30mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:30mm; Sensor Housing:Barrel |
| A42MX36-2BG100ES | 40MX and 42MX FPGA Families |
| A42MX02-2BG100I | 40MX and 42MX FPGA Families |
| A42MX04-2BG100I | 40MX and 42MX FPGA Families |
| A42MX09-2BG100I | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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